Lecture24-Timing-6up

Lecture24-Timing-6up - EE141-Fall 2010 Digital Integrated...

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EE141 1 EECS141 1 Lecture #24 EE141 EE141 -Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 24 Lecture 24 Timing Timing EE141 2 EECS141 2 Lecture #24 Announcements Announcements ± Homework #8 due next Tuesday ± Project Phase 3 plan due this Sat. ± Hanh-Phuc’s extra office hours shifted next week ² Tues. 3-4pm EE141 3 EECS141 3 Lecture #24 Class Material Class Material ± Last lecture ² Latches and flip-flops ± Today’s lecture ² Timing ± Reading ² Chapter 7, 10 EE141 4 EECS141 4 Lecture #24 Timing Timing EE141 5 EECS141 5 Lecture #24 Synchronous Timing Synchronous Timing Combinational Logic R 1 R 2 C in C out Out In CLK EE141 6 EECS141 6 Lecture #24 Latch Parameters D Clk Q D Q Clk t clk-q t hold PW m t setup t d-q Delays can be different for rising and falling data transitions T
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EE141 7 EECS141 7 Lecture #24 Register Parameters Register Parameters D Clk Q D Q Clk t clk-q t hold T t setup Delays can be different for rising and falling data transitions EE141 8 EECS141 8 Lecture #24 R1 DQ Combinational Logic In CLK t CLK1 R2 t CLK2 Cycle time (max): T Clk > t clk-q + t logic + t setup Race margin (min): t hold < t clk-q,min + t logic,min Timing Constraints Timing Constraints t clk-q t clk-q,min t logic t logic,min t setup , t hold EE141 9 EECS141 9 Lecture #24 Clock Clock Nonidealities Nonidealities ± Clock skew ² Spatial variation in temporally equivalent clock edges; deterministic + random, t SK ± Clock jitter ² Temporal variations in consecutive edges of the clock signal; modulation + random noise ²
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Lecture24-Timing-6up - EE141-Fall 2010 Digital Integrated...

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