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Unformatted text preview: EE141 1 EECS141 1 Lecture #26 EE141 EE141-Fall 2010 Fall 2010 Digital Integrated Digital Integrated Circuits Circuits Lecture 26 Lecture 26 I/O Issues I/O Issues Power Distribution Power Distribution EE141 2 EECS141 2 Lecture #26 Announcements Announcements Project phase 3 Poster session tomorrow starting at 3:30pm Final report: Mon. Dec. 6 th 5:00pm Optional HW#9 posted HKN surveys end of this Thurs. lecture Attendance required Final exam: Wed. Dec. 15 th , 8-11:00am, Location TBD Review session most likely on Mon. Dec. 13th EE141 3 EECS141 3 Lecture #26 Class Material Class Material Last lecture Clock distribution Todays lecture I/O Design Power Distribution EE141 4 EECS141 4 Lecture #26 I/O Design I/O Design EE141 5 EECS141 5 Lecture #26 Chip Packaging Chip Packaging Chip L L Bonding wire Mounting cavity Lead frame Pin Bond wires (~25 m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100 m in 0.25 m technology), with large pitch (100 m) Many chips are pad limited EE141 6 EECS141 6 Lecture #26 Pad Frame Pad Frame Layout Die Photo EE141 7 EECS141 7 Lecture #26 Bonding Pad Design Bonding Pad Design...
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- Spring '08
- Integrated Circuit