EE1411EECS1411Lecture #26EE141EE141-Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuitsLecture 26Lecture 26I/O IssuesI/O IssuesPower DistributionPower DistributionEE1412EECS1412Lecture #26AnnouncementsAnnouncementsProject phase 3Poster session tomorrow starting at 3:30pmFinal report: Mon. Dec. 6th5:00pmOptional HW#9 postedHKN surveys end of this Thurs. lectureAttendance requiredFinal exam: Wed. Dec. 15th, 8-11:00am, Location TBDReview session most likely on Mon. Dec. 13thEE1413EECS1413Lecture #26Class MaterialClass MaterialLast lectureClock distributionToday’s lectureI/O DesignPower DistributionEE1414EECS1414Lecture #26I/O DesignI/O DesignEE1415EECS1415Lecture #26Chip PackagingChipLL´Bonding wireMountingcavityLeadframePin•Bond wires (~25µm) are used to connect the package to the chip• Pads are arranged in a frame around the chip• Pads are relatively large (~100µm in 0.25µm technology),with large pitch (100µm)•Many chips are ‘pad limited’EE1416EECS1416Lecture #26Pad FrameLayoutDie Photo
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