Lecture5-SwitchLogic Cntd

Lecture5-SwitchLogic Cntd - EE141 EE141 EECS141 Lecture #5...

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EE141 1 EE141 EECS141 1 Lecture #5 EE141 EECS141 2 Lecture #5 Homework #2 posted First lab this week

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EE141 2 EE141 EECS141 3 Lecture #5 Last lecture Design Rules Introduction to switch logic Today’s lecture Optimization of inverter logic Reading (5.4-5.5) EE141 EECS141 4 Lecture #5 V OL = 0 V OH = V DD V M = f(R n , R p ) V DD V DD V in = V DD V in = 0 V out V out R n R p
EE141 3 EE141 EECS141 5 Lecture #5 t pHL = f(R on C L ) = 0.69 R n C L (a) Low-to-high (b) High-to-low EE141 EECS141 6 Lecture #5 C L In Out For some given C L : How many stages are needed to minimize delay? How to size the inverters? Anyone want to guess the solution?

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EE141 4 EE141 EECS141 7 Lecture #5 Get fastest delay if build one very big inverter So big that delay is set only by self-loading Likely not the problem you’re interested in Someone has to drive this inverter… EE141 EECS141 8 Lecture #5 Need to have a set of constraints Constraints key to: Making the result useful Making the problem have a ‘clean’ solution For sizing problem: Need to constrain size of first inverter
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture5-SwitchLogic Cntd - EE141 EE141 EECS141 Lecture #5...

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