Lecture6-ComplexLogic - EE141 EE141 EECS141 Lecture #6 1...

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EE141 1 EE141 EECS141 1 Lecture #6 EE141 EECS141 2 Lecture #6 Lab 3 this week Midterm on Friday February 19 Open book Covering material from start up to complex logic optimization (this lecture and next)
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EE141 2 EE141 EECS141 3 Lecture #6 Last lecture Sizing inverters Today’s lecture Complex logic Optimizing complex logic Reading (2.3, 3.3.1-3.3.2) EE141 EECS141 4 Lecture #6 Output = f ( In ) Output = f ( In, Previous In )
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EE141 3 EE141 EECS141 5 Lecture #6 At every point in time (except during the switching transients) each gate output is connected to either V DD or V SS via a low resistive path. The outputs of the gates assume at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods). (Will contrast this later to dynamic circuit style.) EE141 EECS141 6 Lecture #6 V DD F(In 1 ,In 2 ,…In N ) In 1 In 2 In N In 1 In 2 In N PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks PUN and PDN functions are complementary
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EE141 4 EE141 EECS141 7 Lecture #6 Y = X if A AND B Y = X if A OR B Transistor switch controlled by its gate signal NMOS switch closes when switch control input is high NMOS transistors pass a “strong” 0 but a “weak” 1 A B X Y X Y A B AND OR EE141 EECS141 8 Lecture #6 PMOS switch closes when switch control is low PMOS transistors pass a “strong” 1 but a “weak” 0 X Y A B A B X Y NOR NAND Y = X if A AND B = A + B Y = X if A OR B = AB
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EE141 5 EE141 EECS141 9 Lecture #6 V DD V DD 0 PDN 0 V DD C L C L PUN V DD 0 V DD - V Tn C L V DD V DD V DD |V Tp | C L S D S D V GS S S D D V GS EE141 EECS141 10 Lecture #6 PUP is the dual to PDN (can be shown using DeMorgan’s Theorems) Static CMOS gates are always inverting A + B = AB AB = A + B AND = NAND + INV
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EE141 6 EE141 EECS141 11 Lecture #6 PDN: G = AB
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Lecture6-ComplexLogic - EE141 EE141 EECS141 Lecture #6 1...

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