Lecture7-Wires - EE141 EE141 EECS141 Lecture #7 1 No lab...

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EE141 1 EE141 EECS141 1 Lecture #7 EE141 EECS141 2 Lecture #7 No lab next week Midterm on Fr Febr 19 6:30-8pm in 2060 Valley LSB Review Session: TBA (most likely on Th)
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EE141 2 EE141 EECS141 3 Lecture #7 Last lecture Optimizing complex logic Today’s lecture Applying what we learned on memory decoders Reading (Ch 6.2, 12.1,12.3) EE141 EECS141 4 Lecture #7 Measure everything in units of t inv (divide by t inv ): p – intrinsic delay (k γ g ) - gate parameter f( W ) LE – logical effort (k) – gate parameter f( W ) f – electrical effort (effective fanout) Normalize everything to an inverter: LE inv =1, p inv = γ t pgate = t inv ( p γ + LE × f )
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3 EE141 EECS141 5 Lecture #7 Compute the path effort: PE = ( Π LE) BF Find the best number of stages N ~ log 4 PE Compute the effective fanout/stage EF = PE 1/ N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *LE/EF Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. EE141
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Lecture7-Wires - EE141 EE141 EECS141 Lecture #7 1 No lab...

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