Lecture12-InverterDelay+Energy

# Lecture12-InverterDelay+Energy - EE141 1 EE141 EECS141 1...

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Unformatted text preview: EE141 1 EE141 EECS141 1 Lecture #12 EE141 EECS141 2 Lecture #12 HW 4 Due Today. New HW today as well. Final Lab next week Project to be launched on Wednesday! Probably is wise to be in class that day. EE141 2 EE141 EECS141 3 Lecture #13 EE141 EECS141 4 Lecture #13 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 V in (V) V out (V) Wider PMOS Wider NMOS Symmetrical EE141 3 EE141 EECS141 5 Lecture #13 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 V in (V) V out (V) Fast PMOS Slow NMOS Fast NMOS Slow PMOS Nominal EE141 EECS141 6 Lecture #13 Not all transistors are alike Impacts parameters such as reliability and performance Define process corners: SS, FF, SF, FS EE141 4 EE141 EECS141 7 Lecture #13 7 EE141 EECS141 8 Lecture #13 We modeled this with: C Discharging a capacitor t p = ln (2) RC EE141 5 EE141 EECS141 9 Lecture #13 Real transistors arent exactly resistors Look more like current sources in saturation Two questions: Which region of IV curve determines delay? How can that match up with the RC model? EE141 EECS141 10 Lecture #13 With a step input: I D V DS V DD V DD /2 V GS = V DD V DD V DD/2 V VSAT Transistor is in (velocity) saturation during entire transition from V DD to V DD /2 EE141 6 EE141 EECS141 11 Lecture #13 In saturation, transistor basically acts like a current source: I DSAT C V OUT V OUT = V DD- (I DSAT /C)t V OUT t V DD V DD /2 t p t p = C(V DD /2)/I DSAT EE141 EECS141 12 Lecture #13 EE141...
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## This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture12-InverterDelay+Energy - EE141 1 EE141 EECS141 1...

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