Lecture13-ComplexCMOS - EE141 EE141 EECS141 Lecture #13 1...

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EE141 1 EE141 EECS141 1 Lecture #13 EE141 EECS141 2 Lecture #13 No more re-grading of Midterm after today Hw 5 due on Friday. Hw 6 posted early next week. You get TWO weeks for this one. Project phase 1 introduced today Actual launch is on Friday Out of town next week We lecture offered by Stanley Fr lecture cancelled – Make-up on Tu March 16 at 3:30pm
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EE141 2 EE141 EECS141 3 Lecture #13 Last lecture Inverter delay Today’s lecture Inverter energy Project launch Optimizing complex CMOS Reading (Ch 5, 6) EE141 EECS141 4 Lecture #13
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EE141 3 EE141 EECS141 5 Lecture #13 t pHL = 0.69 C L R eqn t pLH = 0.69 C L R eqp t pLH t pHL EE141 EECS141 6 Lecture #13 Derived RC model assuming input was a step But input is not a step Transistor turns on gradually Let’s look at gate switching more carefully Use our models to understand the effect of input slope
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EE141 4 EE141 EECS141 7 Lecture #13 One way to analyze slope effect Plug non-linear IV into diff. equation and solve… Simpler, approximate solution: Use V T * model EE141 EECS141 8 Lecture #13 For falling edge at output: For reasonable inputs, can ignore I PMOS Either V ds is very small, or V gs is very small So, output current ramp starts when V in = V T * Could evaluate the integral Learn more by using an intuitive, graphical approach
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EE141 5 EE141 EECS141 9 Lecture #13 For reasonable input slopes: EE141 EECS141 10 Lecture #13 For reasonable input slope Model matches Spice very well Model breaks with very large t r Input looks “DC” – traces out VTC Have other problems here anyways – Short-circuit current
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EE141 6 EE141 EECS141 11 Lecture #13 EE141 EECS141 12 Lecture #13 Switching power Charging/discharging capacitors Leakage power Transistors are imperfect switches Short-circuit power Both pull-up and pull-down on during transition Static currents Biasing currents, in e.g. analog, memory
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EE141 7 EE141 EECS141 13 Lecture #13 One half of the energy from the supply is consumed in the pull-up network, one half is stored on C L Energy from C L is dumped during the 1 0 transition V in V out C L V DD EE141 EECS141 14 Lecture #13 Power = Energy/transition Transition rate = C L V DD 2 f 0 1 = C L V DD 2 f α 0 1 = C switched V DD 2 f Power dissipation is data dependent – depends on the switching probability Switched capacitance C switched = C L 0 1
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EE141 8 EE141 EECS141 15 Lecture #13 Energy consumed in N cycles, E N : E N = C L V DD 2 n 0 1 n 0 1 – number of 0 1 transitions in N cycles EE141 EECS141 16 Lecture #13 Short circuit current usually well controlled Large load Small load
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EE141 9 EE141 EECS141 17 Lecture #13 JS = 10-100 pA/ μ m2 at 25 deg C for 0.25 μ m CMOS JS doubles for every 9 deg C! Much smaller than transistor leakage in deep submicron
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture13-ComplexCMOS - EE141 EE141 EECS141 Lecture #13 1...

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