Lecture16-Ratioed+Dynamic

Lecture16-Ratioed+Dynamic - EE141 1 EE141 EECS141 1...

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Unformatted text preview: EE141 1 EE141 EECS141 1 Lecture #16 EE141 EECS141 2 Lecture #16 Project Phase 1 Done – Thanks for the timely response. Phase 2 to be announced We – Launched on Fr. Hw 6 due on Fr. EE141 2 EE141 EECS141 3 Lecture #16 Last lecture Pass transistor logic CMOS Layout Today’s lecture Ratioed Logic Dynamic Logic Reading (Ch 6) EE141 EECS141 4 Lecture #16 EE141 3 EE141 EECS141 5 Lecture #16 EE141 EECS14 6 #16 Goal: build gates faster/smaller than static complementary CMOS EE141 4 EE141 EECS141 7 Lecture #16 Rising and falling delays aren’t the same Calculate LE for the two edges separately For tpLH: C gate = WC G C inv = (3/2)WC G LE LH = EE141 EECS141 8 Lecture #16 What is LE for t pHL ? Switch model would predict R eff = R n ||R p Would that give the right answer for LE? EE141 5 EE141 EECS141 9 Lecture #16 Time constant is smaller, but it takes more time to complete 50% V DD transient (arguably) Rp actually takes some current away from discharging C v o (t)/V DD t Rp=Rn Rp=2Rn Rp=4Rn Rp= ∞ EE141 EECS141 10 Lecture #16 Think in terms of the current driving C load When you have a conflict between currents Available current is the difference between the two In pseudo-nMOS case: (Works because Rp >> Rn for good noise margin) EE141 6 EE141 EECS141 11 Lecture #16 For t pHL (assuming R sqp = 2R sqn ): R gate = R n /(1-Rn/Rp) = 2Rn R inv = R n C gate = WC G C inv = 3WC G LE HL = LE is lower than an inverter!...
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Lecture16-Ratioed+Dynamic - EE141 1 EE141 EECS141 1...

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