Lecture17-Domino+Registers

Lecture17-Domino+Registers - EE141 1 EE141 EECS141 1...

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Unformatted text preview: EE141 1 EE141 EECS141 1 Lecture #17 EE141 EECS141 2 Lecture #17 Phase 2 announced. Launched in the next 24 hours. Hw 6 due on Fr. EE141 2 EE141 EECS141 3 Lecture #17 Last lecture Ratioed Logic Dynamic Logic Today’s lecture Domino Logic Registers Reading (Ch 6, Ch 7) EE141 EECS141 4 Lecture #17 EE141 3 EE141 EECS141 5 Lecture #17 Goals: - Design bit-node so that clock frequency is minimized - Layout bit and check nodes Due Date: Wednesday April 13 EE141 EECS141 6 Lecture #16 EE141 4 EE141 EECS141 7 Lecture #16 In 1 In 2 PDN In 3 M e M p Clk Clk Out C L Out Clk Clk A B C M p M e Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 off on ((AB)+C) EE141 EECS141 8 Lecture #16 Noise sensitivity and small noise margins Leakage Charge sharing Clock feedthrough EE141 5 EE141 EECS141 9 Lecture #16 C L Clk Clk B A Out M p M e Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD . The fast rising (and falling edges) of the clock couple to Out....
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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Lecture17-Domino+Registers - EE141 1 EE141 EECS141 1...

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