Lecture18-Registers - EE141 1 EE141 EECS141 1 Lecture #18...

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Unformatted text preview: EE141 1 EE141 EECS141 1 Lecture #18 EE141 EECS141 2 Lecture #18 Project Phase 2 now on the web-site. Hw 6 due today. New homework to be posted in a week. Cory Hall closed on Monday (Power Outage) Instructional computers in 353 Cory should come back on line on Tu. Enjoy Spring Break! EE141 2 EE141 EECS141 3 Lecture #18 Last lecture Domino Logic Introduction to registers Todays lecture Registers Timing Reading (Ch 7) EE141 EECS141 4 Lecture #16 EE141 2 EE141 EECS141 3 Lecture #18 Last lecture Domino Logic Introduction to registers Todays lecture Registers Timing Reading (Ch 7) EE141 EECS141 4 Lecture #16 EE141 3 EE141 EECS141 5 Lecture #16 Output = f ( In ) Output = f ( In, Previous In ) EE141 EECS141 6 Lecture #16 D Clk Q D Clk Q Register: edge-triggered stores data when clock rises Clk Clk D D Q Q Latch: level-sensitive clock is low - hold mode clock is high - transparent EE141 4 EE141 EECS141 7 Lecture #16 Register Latch Clk D Q t C Q Clk D Q t C Q t D Q EE141 EECS141 8 Lecture #16 t CLK t D t c q t hold t su t Q DATA STABLE DATA STABLE Register CLK D Q EE141 5 EE141 EECS141 9 Lecture #16 D CLK CLK Q Dynamic Static EE141 EECS141 10 Lecture #16 EE141...
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Lecture18-Registers - EE141 1 EE141 EECS141 1 Lecture #18...

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