Lecture19-Timing

Lecture19-Timing - EE141 EE141 EECS141 Lecture#19 1 Project...

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EE141 1 EECS141 1 Lecture #19 EECS141 2 Lecture #19 Project Phase 2 now on the web-site. Hw 6 due today. New homework to be posted in a week. Cory Hall closed on Monday (Power Outage) Instructional computers in 353 Cory should come back on line on Tu. Enjoy Spring Break!
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EE141 2 EECS141 3 Lecture #19 Last lecture Registers Today’s lecture Timing Reading (Ch 10) EECS141 4 Lecture #16
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EE141 3 EECS141 5 Lecture #16 D Clk Q D Clk Q Register: edge-triggered stores data when clock rises Clk Clk D D Q Q Latch: level-sensitive clock is low - hold mode clock is high - transparent EECS141 6 Lecture #16
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EE141 4 EECS141 7 Lecture #16 D Clk Q D Q Clk t clk-q t hold PW m t setup t d-q Delays can be different for rising and falling data transitions T EECS141 8 Lecture #16 D Clk Q D Q Clk t clk-q t hold T t setup Delays can be different for rising and falling data transitions
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EE141 5 EECS141 9 Lecture #16 t clk-q t clk-q,min t logic t logic,min t setup , t hold EECS141 10 Lecture #16 Cycle time (max): T Clk > t clk-q + t logic + t setup Race margin (min): t hold < t clk-q,min + t logic,min t clk-q t clk-q,min t logic t logic,min t setup , t hold
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EE141 6 EECS141 11 Lecture #16 Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width Important for level sensitive clocking EECS141 12 Lecture #16 Sources of clock uncertainty
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EE141 7 EECS141 13 Lecture #16
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