Lecture20-Scaling

Lecture20-Scaling - EE141 EE141 EECS141 Lecture#20 1...

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EE141 1 EE141 EECS141 1 Lecture #20 EE141 EECS141 2 Lecture #20 Midterm 2 on We April 7 6:30-8pm in 277 Cory Open book. Covers everything until Lecture 17 (DOMINO LOGIC). Registers and timing NOT included. Review Session: Tu April 6 6:30-8pm in 289 Cory DO NOT FORGET THE PROJECT! Extra office hours of TAs on Mo and Tu (during lab hours) in 353 Cory Project Phase 1 has been graded. Results will be posted early next week.
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EE141 2 EE141 EECS141 3 Lecture #20 Last lecture Timing Today’s lecture Technology Scaling Reading (Ch 5) EE141 EECS141 4 Lecture #20
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EE141 3 EE141 EECS141 5 Lecture #20 Cycle time (max): T Clk > t clk-q + t logic + t setup Race margin (min): t hold < t clk-q,min + t logic,min t clk-q t clk-q,min t logic t logic,min t setup , t hold EE141 EECS141 6 Lecture #20 If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic t clk-q + t logic + t setup < T CLK – t JS,1 – t JS,2 + δ t clk-q + t logic + t setup - + 2t JS < T CLK Skew can be either positive or negative
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EE141 4 EE141 EECS141 7 Lecture #20 Minimum logic delay
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This note was uploaded on 02/06/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at Berkeley.

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Lecture20-Scaling - EE141 EE141 EECS141 Lecture#20 1...

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