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Lecture25-Memory

Lecture25-Memory - EE141 EE141 EECS141 Lecture#25 1 Hw 8...

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EE141 1 EECS141 1 Lecture #25 EECS141 2 Lecture #25 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
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EE141 2 EECS141 3 Lecture #25 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 Frequency [GHz] Performance Histogram EECS141 4 Lecture #25 0 1 2 3 4 1.5 2 2.5 3 3.5 Frequency [GHz] 0.0E+00 5.0E-04 1.0E-03 1.5E-03 2.0E-03 2.5E-03 3.0E-03 3.5E-03 0.0E+00 1.0E+09 2.0E+09 3.0E+09 Power [W] Frequency [Hz] Performance - pruned
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EE141 3 EECS141 5 Lecture #25 Max: 98 Avg: 78.9 StDev: 12.9 Median: 81 0 1 2 3 4 5 6 50 60 70 80 90 100 EECS141 6 Lecture #25 Design implementation of 256-bit code Create floorplan to estimate wirelength Optimize circuit such that energy is minimized for max delay of 10 nsec Determine also Tdmin and Emin for that design Present results in poster Energy Delay (T d,max , E min ) (T d,min , E max ) (T d , E)
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EE141 4 EECS141 7 Lecture #25 Template: Group A: Group B: Same but period is 4 Group C: Same but period is 8 Group D: Same but period is 16 EECS141 8 Lecture #25
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EE141 5 EECS141 9 Lecture #25 EECS141 10 Lecture #25 Energy Delay 10ns ? Joule Optimization target The extremes
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EE141 6 EECS141 11 Lecture #25 Last lecture Multipliers Today’s lecture Memory cells Reading (Ch 12) EECS141 12 Lecture #25 12
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EE141 7 EECS141 13 Lecture #25 Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO EECS141 14 Lecture #25 STATIC (SRAM) DYNAMIC (DRAM) Data stored as long as supply is applied Larger (6 transistors/cell) Fast Differential (usually) Periodic refresh required Smaller (1-3 transistors/cell) Slower Single Ended
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EE141 8 EECS141 15 Lecture #25 Conceptual: linear array Each box holds some data But this does not lead to a nice layout shape Too long and skinny Create a 2-D array Decode Row and Column address to get data EECS141 16 Lecture #25 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage cell M bits M bits N words S 0 S 1 S 2 S N-2 A 0 A 1 A K-1 K = log 2 N S N -1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage cell S 0 Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output ( M bits) D e c o d e r
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EE141 9 EECS141 17 Lecture #25 EECS141 18 Lecture #25 • If D is high, D_b will be driven low • Which makes D stay high • Positive feedback
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