Verification_Plan_Template

Verification_Plan_Template - Page 1 of 7 Chip-level...

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Unformatted text preview: Page 1 of 7 Chip-level [Chipname] [Blockname] Test Plan Template Author: [Name], Equator Technologies, Inc. 1.0 System Description - Required 1.1 Summary of System Functionality Action: List and paraphrase the function of each new, changed or re-used block Intent: Provide overview and scope of functions to be verified 1.2 System Block Diagram Action: Provide a block diagram of the Design Under Verification; use a color or shading system to identify re-used, changing, and/or new blocks. Intent: Provide visual aid to “Summary of System Functionality” of Design Under Verification 1.3 Relevant DUV Specification Version Action: Name the specification(s) and spec(s) version(s) used to create test plan Intent: Provide a reference to the local or industry standard specification(s) used for verification-ori- ented interpretations 1.4 Previous Project(s) Verification Problem Area(s) Carry-forward Action: List problem(s) encountered in verifying previous project(s) Intent: Encourage resolution and/or warn of existing problem area 1.5 Acronyms Used in Test Plan Action: Define acronyms used in test plan document Intent: Provide clarity to the reader and documentation efficiency to the writer 2.0 Chip-level First-Pass Design Verification Success Criteria Action: List first-pass verification success criteria in terms of testcase and testbench development Table 1: List of System Blocks including re-used, new, and changed Block Name Name of Function(s) Status (New/ Changed) Explanation of Function(s) to be tested Block XY Status Reg- ister A Changed 3 new status bits; (1) last reset was a system reset, (2) transaction ongoing, and (3) transaction fin- ished State machine B New Internal bus protocol state machine Block Z ABC Con- trol Regis- ter bit 0 Changed Reset value changed from 0 to 1 Chip-level [Chipname] [Blockname] Test Plan Template Page 2 of 7 Intent: Plan for verification of design first pass success 2.1 Testcase Generation Plan Action: Explain what new chip-level testcase generation will be required Intent: Plan chip-level testcase need for the block under test 2.1.1 Current Testcases Update - Required Action: Analyze current testcases for extent of re-usability Intent: Provide prioritized list of testcases which will require update in order to be useful as verifica- tion software for the current design project 2.1.2 Testcase Types Plan for New Testcases - Required Action: Plan for types of chip-level testing to be used in new testcases Intent: Consider the design changes and new design and what is required to test it 2.1.2.1 Feature or Function Action: Plan for the types of Feature/Functional testing to be employed or not and why Intent: Arrive at an overview or vision of chip-level functional/feature testing needed for the block 2.1.2.1.1 Internal (check computation) Action: Plan for Internal checking to be done or not done and why Intent: Determine extent of need for Internal testing 2.1.2.1.2 External (check interface) Action: Plan for External checking testcases to be done or not done and why...
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Verification_Plan_Template - Page 1 of 7 Chip-level...

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