10-Exceptions

10-Exceptions - 3/15/2010 1 Reset, Interrupts, Exceptions,...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 3/15/2010 1 Reset, Interrupts, Exceptions, and Break ECE 2534 1 Packet 10 Reset, Interrupts, Exceptions, Break These topics are closely related Both software and hardware aspects of a Both software and hardware aspects of a processor are involved On the MicroBlaze, the facilities to handle them are quite similar All of these refer to mechanisms for altering the normal execution of a program 2 Usual purpose: get the processors attention for something that cant wait Reading: relevant parts of Chapter 1 in MBlaze Reference Guide 3/15/2010 2 For the MicroBlaze, these things are prioritized: Reset ( highest priority) Reset ( highest priority) Hardware Exception Non-maskable Break Breaks Interrupts 3 Interrupts User Vectors (Exceptions) (Yes, the Xilinx terminology is a little confusing at first) Interrupts and Exceptions These concepts are closely related, and the terminology is sometimes blurred (An interrupt is often considered to be a type of exception!) Deviation in normal sequence of actions For our purposes 4 For our purposes, An interrupt is asynchronous, traditionally generated by some external hardware device An exception is synchronous, resulting directly from the most recent instruction (example: divide-by-zero) 3/15/2010 3 Typical sequence of actions (1/2) A triggering event occurs CPU finishes executing the current instruction CPU may save the state of the processor (PC, MSR, other registers) 5 CPU may update status registers CPU branches to service routine (the MBlaze does this through its vector table) Vector Table in MicroBlaze 6 3/15/2010 4 Typical sequence of actions (2/2) The CPU executes instructions in the appropriate service routine appropriate service routine The service routine terminates with the appropriate instruction: rtid (return from interrupt) rted (return from exception) tbd (return from break 7 rtbd (return from break) By executing this instruction, the CPU may update status registers the CPU changes the PC No return from a reset! Notice . . ....
View Full Document

Page1 / 16

10-Exceptions - 3/15/2010 1 Reset, Interrupts, Exceptions,...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online