CD22402 - Semiconductor May 1999 T NT DUC PRO LACEME 747 ETE REP-7 OL-442 OBS ENDED-800 com 1 M ons arris COM icati O RE ral Appl [email protected] N n Sync

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8-40 Semiconductor May 1999 CD22402 Sync Generator for TV Applications and Video Processing Systems Features • Interlaced Composite Sync Output • Automatic Genlock Capability • Crystal Oscillator Operation • 525 or 625 Line Operation • Vertical Reset Option • Wide Power Supply Operating Voltage . . . . . 4V to 15V Applications • Cameras • Monitors and Displays •CA TV • Teletext • Video Games • Sync Restorer • Video Service Instruments Description The Harris CD22402 (Note) is a CMOS LSI sync generator that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/sec- ond TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval. The CD22402 can be operated either in “genlock” mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in “stand-alone” mode, in which it is syn- chronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the “genlock” or “stand-alone” mode. A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. The interlaced sync provided by the CD22402 differs from RS-170 by having slightly narrower sync and equalizing pulses. The clock frequency of 32 times horizontal rate allows for approximately 4 μ s horizontal pulse widths and 2 μ s equalizing pulses. Otherwise operation can be phase locked to a color sub-carrier for a full interlaced operating system. The CD22402 is operable with a single supply over a voltage range of 4V to 15V. Pinout CD22402 (PDIP, SBDIP) TOP VIEW Part Number Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD22402D -55 to 125 24 Ld SBDIP D24.6 CD22402E -40 to 85 24 Ld PDIP E24.6 1 2 3 4 5 6 7 8 9 10 11 12 MIXED SYNC OUTPUT VERTICAL DRIVE OUTPUT HORIZONTAL CLAMP OUTPUT 16 17 18 19 20 21 22 23 24 15 14 13 FRAME SYNC OUTPUT (ODD FIELD) HORIZONTAL PROCESSING BLANKING OUTPUT MIXED PROCESSING BLANKING OUTPUT MASTER FREQUENCY INPUT DELAY, GENLOCK TO CRYSTAL OSCILLATOR CRYSTAL OSCILLATOR FEEDBACK TAP HORIZONTAL DRIVE OUTPUT MIXED BEAM BLANKING OUTPUT GENLOCK OSCILLATOR CAPACITOR CONNECTION VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE VERTICAL RESET TO FIRST VERTICAL SYNC PULSE SHORT VERTICAL DRIVE OUTPUT 525 LINE TO 625 LINE OPERATION SWITCH VERTICAL PROCESSING BLANKING OUTPUT R-C CONNECTION FOR GENLOCK OSCILLATOR DELAY, GENLOCK TO CRYSTAL OSCILLATOR GENLOCK INPUT (COMPOSITE SYNC) RESISTOR CONNECTION FOR GENLOCK OSCILLATOR V SS V SS V DD CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
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This note was uploaded on 02/08/2011 for the course EE 459L taught by Professor Weber during the Spring '11 term at USC.

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CD22402 - Semiconductor May 1999 T NT DUC PRO LACEME 747 ETE REP-7 OL-442 OBS ENDED-800 com 1 M ons arris COM icati O RE ral Appl [email protected] N n Sync

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