TIM08RM

TIM08RM - Freescale Semiconductor, Inc. TIM08RM/AD Rev. 1.0...

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Unformatted text preview: Freescale Semiconductor, Inc. TIM08RM/AD Rev. 1.0 Freescale Semiconductor, Inc... HC 8 TIM08 TIMER INTERFACE MODULE REFERENCE MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. REQUIRED Freescale Semiconductor, Inc... TIM08 Timer Interface Module Reference Manual © Motorola, Inc., 1996; All Rights Reserved For More Information On This Product, Go to: www.freescale.com NON-DISCLOSURE AGREEMENT Freescale Semiconductor, Inc. REQUIRED NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. List of Sections Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Freescale Semiconductor, Inc... Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16-Bit Modulo Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 153 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . 155 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 TIM08 Reference Manual — Rev. 1.0 MOTOROLA List of Sections For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. List of Sections Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 6 List of Sections For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Revision History Revision History This table summarizes differences between this revision and the previous revision of this reference manual. Previous Revision Current Revision Original Release 1.0 08/96 Format and organizational changes Incorporated changes reflected in Addendum (TIM08RMAD/AD) Throughout Freescale Semiconductor, Inc... Date Changes Location TIM08 Reference Manual — Rev. 1.0 MOTOROLA For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Preface All M68HC08 microcontrollers are modular, customer-specified designs. To meet customer requirements, Motorola is constantly designing new modules and creating new versions of exisitng modules. Freescale Semiconductor, Inc... The TIM08 Reference Manual introduces version B of the TIM08, the timer interface module of the Motorola HC08 Family. Future versions of the TIM08 will be attached as appendices in this reference manual. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Preface For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. Preface Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 10 Preface For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table of Contents Overview Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Freescale Semiconductor, Inc... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Input Capture (IC) Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Output Compare (OC) Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Unbuffered Output Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Buffered Output Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Pulse-Width Modulation (PWM) Concepts . . . . . . . . . . . . . . . . . . . . .30 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . .32 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . .33 Signal Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Input Capture/Output Compare Pins (TCH0, TCH1, TCH2, TCH3) . .36 Input Capture Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Output Compare Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PWM Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Auxiliary Timer Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . .38 Prescaler Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .41 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. Table of Contents 16-Bit Modulo Counter Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Timer Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Freescale Semiconductor, Inc... Capture/Compare Unit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Input Capture (IC) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .60 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Unbuffered Output Compare (OC) Functions . . . . . . . . . . . . . . . . . . .65 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .67 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Buffered Output Compare (OC) Functions . . . . . . . . . . . . . . . . . . . . .72 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . . . . .75 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Unbuffered Pulse Width Modulation (PWM) Functions . . . . . . . . . . .80 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .83 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Buffered Pulse Width Modulation (PWM) Functions . . . . . . . . . . . . .90 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .94 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . . . . . . . . .102 TIM08 Reference Manual — Rev. 1.0 12 Table of Contents For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Table of Contents CPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Timer Overflow Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Output Compare/PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . .109 DMA Service Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Output Compare/PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . .113 Special Modes Freescale Semiconductor, Inc... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Applications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 General TIM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 PWM Controlled RC Digital to Analog Converter . . . . . . . . . . . . . . .131 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Servo Loop Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Using the HC708XL36 DMA with the TIM . . . . . . . . . . . . . . . . . . . .144 Functional Description of Program . . . . . . . . . . . . . . . . . . . . . . .146 System Resource Configuration . . . . . . . . . . . . . . . . . . . . . . . . .146 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Table of Contents For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. Table of Contents Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Memory Map and Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Freescale Semiconductor, Inc... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .156 Timer DMA Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Timer Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .161 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . . . .162 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Pin Summary Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 TIM Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 TIM Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Glossary Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 TIM08 Reference Manual — Rev. 1.0 14 Table of Contents For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... Figure 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Title Page TIM Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Input Capture Simplified Block Diagram. . . . . . . . . . . . . . . .25 Output Compare Simplified Block Diagram . . . . . . . . . . . . .27 Buffered Output Compare Simplified Block Diagram . . . . . .29 Pulse-Width Modulation Example . . . . . . . . . . . . . . . . . . . .30 Pulse-Width Modulation Simplified Block Diagram . . . . . . .31 Buffered PWM Simplified Block Diagram . . . . . . . . . . . . . . .34 Function Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Prescaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .40 TCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Timer Status and Control Register (TSC) . . . . . . . . . . . . . .41 TSTOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 16-Bit Modulo Counter Simplified Block Diagram . . . . . . . .48 Timer Status and Control Register (TSC) . . . . . . . . . . . . . .49 TSTOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Timer Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . .53 Timer Counter Modulo Registers (TMODH:TMODL) . . . . . .54 Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Timer Channel Status and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . . .60 Timer Channel Register (TCH0H/L–TCH3H/L) . . . . . . . . . .64 Unbuffered Output Compare Timing . . . . . . . . . . . . . . . . . .66 Timer Channel Status and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . . .67 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .71 Buffered Output Compare Timing . . . . . . . . . . . . . . . . . . . .74 Timer Channel Status and Control Register (TSC0 and TSC2) . . . . . . . . . . . . . . . . . . . . . . .75 TIM08 Reference Manual — Rev. 1.0 MOTOROLA List of Figures For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. List of Figures Table 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 TIM08 Reference Manual — Rev. 1.0 16 List of Figures For More Information On This Product, Go to: www.freescale.com MOTOROLA Title Page Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .79 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . .80 Unbuffered PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Timer Channel Status and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . . .84 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .89 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . .90 Buffered PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Timer Channel Status and Control Registers (TSC0, TSC2) . . . . . . . . . . . . . . .94 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . .99 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . .102 CPU Counter Overflow Interrupt Timing Example A . . . . .106 CPU Counter Overflow Interrupt Timing Example B . . . . .107 CPU Input Capture Interrupt Timing Example . . . . . . . . . .108 CPU Output Compare/PWM Interrupt Example . . . . . . . . .110 DMA Input Capture Service Request Timing Example . . .112 DMA Output Compare/PWM Service Request Example . .114 RC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 25% Duty Cycle PWM Signal . . . . . . . . . . . . . . . . . . . . . . .131 10 kHz, 50% Duty Cycle RC Transient Response . . . . . . .133 10-kHz, 50% Duty Cycle RC Response . . . . . . . . . . . . . . .134 Buffered Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 PD Loop Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Servo Loop Motor Control Block Diagram . . . . . . . . . . . . .140 Waveform On Output Compare Pin (PTE5) . . . . . . . . . . . .145 Internal Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Timer Status and Control Register (TSC) . . . . . . . . . . . . .156 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . .158 Timer Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . .160 Timer Counter Modulo Registers (TMODH:TMODL) . . . . .161 Timer Channel Status and Control Registers (TSC0–TSC3) . . . . . . . . . . . . . .163 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Timer Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . .169 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Tables Table 1 2 Title Page Prescaler Selection.................................................................45 Input Capture Mode and Edge Selection................................62 Unbuffered Output Compare Mode and Level Selection........70 Buffered Output Compare Mode and Level Selection ............77 Unbuffered PWM Mode and Level Selection..........................86 Buffered PWM Mode and Level Selection..............................96 TIM Interrupt Priority.............................................................104 Range and Resolution for Period Input/Output* ...................121 Output Voltages....................................................................134 Output Compare Values .......................................................145 AC Characteristics................................................................153 Prescaler Selection...............................................................157 Mode, Edge, and Level Selection.........................................166 Pin Functions........................................................................171 TCH0 and TCH2 Pins...........................................................172 TCH1 and TC H3 Pins..........................................................173 TCLK Pin ..............................................................................173 Freescale Semiconductor, Inc... 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TIM08 Reference Manual — Rev. 1.0 MOTOROLA List of Tables For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 18 List of Tables For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Freescale Semiconductor, Inc... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Input Capture (IC) Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Output Compare (OC) Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Unbuffered Output Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Buffered Output Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Pulse-Width Modulation (PWM) Concepts . . . . . . . . . . . . . . . . . . . . .30 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . .32 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . .33 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. Overview Introduction The timer interface module (TIM), a module in Motorola's HC08 Family of modular microcontrollers, is a simple yet flexible timer for use in systems where a moderate level of CPU control is required. The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. The TIM can be broken into several submodules: the prescaler, the 16-bit modulo counter, and the capture/compare unit. Figure 1 shows the major submodules of the TIM, the external pins associated with the TIM, and the internal bus signals used by the TIM. EXTERNAL MCU BUS PORT PIN PORT PIN PORT PIN PORT PIN TCH0 TCH1 TCH2 TCH3 CAPTURE/COMPARE UNIT INTERNAL MCU BUS TCH0 INTERRUPT TCH1 INTERRUPT TCH2 INTERRUPT TCH3 INTERRUPT INTERNAL ADDRESS BUS 16-BIT COUNTER TOV INTERRUPT INTERNAL DATA BUS PORT PIN TCLK PRESCALER IT12 BUS CLOCKS IT23 Freescale Semiconductor, Inc... } Figure 1. TIM Submodules Figure 2 shows the structure of the TIM. The central component of the TIM is the 16-bit counter that can operate as a free-running counter or a modulo up-counter. The timer counter provides the timing reference for the input capture, output compare, and pulse-width modulation functions provided by the capture/compare unit. The timer counter modulo registers, TMODH:TMODL, control the modulo value of the timer counter. Software can read the timer counter value from the timer counter registers, TCNTH:TCNTL, at any time without affecting the counting sequence. TIM08 Reference Manual — Rev. 1.0 20 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Introduction The capture/compare unit features two, four, six, or eight channels. These channels share the 16-bit counter (TCNTH:TCNTL) which receives its clock input from the six-stage prescaler or from the external clock input pin, TCLK. Each channel can be programmed as either an input capture channel, an unbuffered output compare channel, or an unbuffered pulse-width modulation channel. Two channels may be combined to provide one buffered output compare channel or one buffered pulse-width modulation channel. If not needed for timing functions, any of the TIM pins can be used as general-purpose bidirectional input/output (I/O) port pins. Figure 2 shows the registers in the TIM. Freescale Semiconductor, Inc... NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. Overview TCLK PRESCALER SELECT BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL PRESCALER PS2 PS1 PS0 TOF TOE INTERRUPT LOGIC Freescale Semiconductor, Inc... TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 CHANNEL 1 DATA BUS 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1F DMA1S CH1IE TOV2 CHANNEL 2 16-BIT COMPARATOR TCH2H:TCH2L 16-BIT LATCH MS2A MS2B TOV3 CHANNEL 3 16-BIT COMPARATOR TCH3H:TCH3L 16-BIT LATCH MS3A CH3F DMA3S CH3IE INTERRUPT LOGIC ELS3B ELS3A CH3MAX PORT LOGIC TCH3 CH2F DMA2S CH2IE INTERRUPT LOGIC ELS2B ELS2A CH2MAX PORT LOGIC TCH2 INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 CH0F DMA0S CH0IE INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0 Figure 2. TIM Block Diagram TIM08 Reference Manual — Rev. 1.0 22 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Introduction 7 TIMER STATUS AND CONTROL REGISTER (TSC) TIMER DMA SELECT REGISTER (TDMA) TOF 0 6 5 4 3 0 2 PS2 1 PS1 0 PS0 TOE TSTOP TRST 0 0 0 DMA3S DMA2S DMA1S DMA0S BIT 8 BIT 0 BIT 8 BIT 0 TIMER COUNTER REGISTER HIGH (TCNTH) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 TIMER COUNTER REGISTER LOW (TCNTL) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 TIMER MODULO REGISTER HIGH (TMODH) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 TIMER MODULO REGISTER LOW (TMODL) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 CHANNEL 0 STATUS AND CONTROL REGISTER (TSC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX CHANNEL 0 REGISTER HIGH (TCH0H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 CHANNEL 0 REGISTER LOW (TCH0L) BIT 7 BIT 6 BIT 5 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8 BIT 0 CHANNEL 1 STATUS AND CONTROL REGISTER (TSC1) CH1F CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX BIT 8 BIT 0 Freescale Semiconductor, Inc... CHANNEL 1 REGISTER HIGH (TCH1H) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 CHANNEL 1 REGISTER LOW (TCH1L) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 CHANNEL 2 STATUS AND CONTROL REGISTER (TSC2) CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX CHANNEL 2 REGISTER HIGH (TCH2H) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 CHANNEL 2 REGISTER LOW (TCH2L) BIT 7 BIT 6 BIT 5 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8 BIT 0 CHANNEL 3 STATUS AND CONTROL REGISTER (TSC3) CH3F CH3IE MS3A ELS3B ELS3A TOV3 CH3MAX BIT 8 BIT 0 CHANNEL 3 REGISTER HIGH (TCH3H) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 CHANNEL 3 REGISTER LOW (TCH3L) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Figure 2. TIM Block Diagram (Concluded) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. Overview Features • • Modular Architecture Up to Eight Input Capture Channels – Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger • Up to Eight Unbuffered Output Compare Channels or Four Buffered Output Compare Channels – Set, Clear, or Toggle Output Compare Action Freescale Semiconductor, Inc... Toggle Any Channel Pin on Counter Overflow • Up to Eight Unbuffered Pulse Width Modulation (PWM) Channels or Four Buffered PWM Channels – 100% Duty Cycle Capability – Set, Clear, or Toggle Action on Pulse Width Match – Toggle Any Channel Pin on Counter Overflow • Programmable TIM Clock Input – 7-Frequency Bus Clock Prescaler Selection – External TIM Clock Input • • • • Free-Running or Modulo Up-Count Operation Timer Counter Stop and Reset Bits CPU Interrupt Generation DMA Service Request Generation on Microcontrollers Containing a DMA Module TIM08 Reference Manual — Rev. 1.0 24 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Input Capture (IC) Concepts Input Capture (IC) Concepts An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter. The edge select logic determines the type of input transition to which the circuit responds. When an input transition occurs, an input capture function latches the contents of the counter into the input capture latch. This action sets a status flag indicating that an input capture has occurred. (See Figure 3.) Freescale Semiconductor, Inc... When the status flag is set, an interrupt is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this value is stored in the input capture register when the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. CLOCK 16-BIT COUNTER EVENT EDGE SELECT LOGIC SELECTED EDGE INPUT CAPTURE LATCH DATA BUS Figure 3. Input Capture Simplified Block Diagram Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. If interrupts are enabled, an interrupt can be directed to the CPU, or a service request can be directed to the DMA, when available. If the status flag is being polled by the software, an input capture subroutine can be executed when the status flag is set. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. Overview By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. For example, to measure the high time of a pulse, the input transition is captured at the rising edge and subtracted from the time captured for the subsequent falling edge. When the period or pulse width is less than the 16-bit modulo counter overflow period, the measurement is very straightforward. In practice, however, software usually must track the overflows of the 16-bit modulo counter to extend its range. Freescale Semiconductor, Inc... Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal, a specific number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to this captured value and stored to an output compare register. Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Output Compare (OC) Concepts Output compare functions are used to program a specific time an event occurs. An output compare function has a 16-bit compare register and a 16-bit comparator. A 16-bit modulo counter provides the timing reference for output compares. When the contents of the compare register match the value of the counter, the comparator sets an output compare flag. (See Figure 4.) Other events can occur when the flag is set. An interrupt can be generated if enabled. State changes can optionally occur on pins associated with the output compare function. TIM08 Reference Manual — Rev. 1.0 26 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Output Compare (OC) Concepts CLOCK 16-BIT COUNTER 16-BIT OUTPUT COMPARE REGISTER 16-BIT COMPARATOR = Freescale Semiconductor, Inc... OUTPUT MATCH Figure 4. Output Compare Simplified Block Diagram Software can determine that an output compare match has occurred by enabling output compare interrupts or by polling the status flag bit. If interrupts are enabled, an interrupt can be directed to the CPU, or a service request can be directed to the DMA, when available. If the status flag is being polled by the software, an output compare subroutine can be executed when the status flag is set. The output compare function can generate an output of a specific duration and polarity. A 16-bit value corresponding to the time a pin state change will occur is written to the output compare register. The output compare function is configured to automatically generate a high or low output on the pin or toggle its state when the match occurs. The output compare register can be reprogrammed to a new value after the compare occurs. The new value corresponds to the time the next compare occurs. When the next match takes place, the pin automatically changes to the specified state. The output compare pin can also be configured to toggle its state when the 16-bit modulo counter overflows. Because pin state changes occur automatically at specific values of the counter, the pulse width can be controlled to the resolution of the counter independent of software latencies. A periodic pulse of a specific frequency and duty cycle can be generated by repeating the preceding steps. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. Overview Unbuffered Output Compares Any TIM channel can generate unbuffered output compare pulses. The signal is unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the channel registers. An unsynchronized write to the channel registers to change a pulse width could cause incorrect operation for up to two counter periods. For example, if a new output compare value is written to the compare registers before the previous output compare match occurred, but after the counter had reached the new value, no output compare match would occur during that counter period. Or if a new, small value is written during a timer overflow interrupt routine, but the output compare match is missed because the new value is not written until after the timer counter has passed that value, no output compare match would occur during that counter period. The output compare interrupt occurs at the end of the current pulse, while the timer overflow interrupt occurs at the end of the current period. In applications that cannot tolerate erroneous data during output compare pulse width changes, two methods are used to synchronize an unbuffered output compare pulse width. When changing to a longer pulse width, enable timer overflow interrupts and write the new pulse width during the timer overflow interrupt routine. When changing to a shorter pulse width, enable output compare interrupts and write the new pulse width value during the output compare interrupt routine. Freescale Semiconductor, Inc... Buffered Output Compares A buffered output compare eliminates the synchronization problem inherent in the unbuffered output compare by providing two channel registers in which to store compare values. In this method, the current output compare value is contained in the first channel register, while a new output compare value is written into the second channel register. On counter overflow, the second channel register value is used to generate the output compare match. By writing new output compare match values only to the unused channel register, erroneous waveforms can be eliminated. Two TIM channels can be linked to form one buffered output compare channel. When the contents of compare register A match the value of TIM08 Reference Manual — Rev. 1.0 28 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Output Compare (OC) Concepts the counter, the comparator sets an output compare flag. Compare register A is used as the output compare value until a new value is written to output compare register B. At the next counter overflow, control switches from output compare register A to output compare register B. Control continues to switch between output compare registers A and B as a new value is written to each register. All control functions and output occur on channel A. The channel B control register is unused, and output pin B reverts to port control. (See Figure 5.) NOTE: Freescale Semiconductor, Inc... In buffered output compare mode, do not write new compare values to the currently active channel registers. The software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compare signals. 16-BIT CHANNEL REGISTER A 16-BIT COMPARATOR A MATCH A CLOCK 16-BIT MODULO COUNTER SELECT OUTPUT 16-BIT COMPARATOR B MATCH B 16-BIT CHANNEL REGISTER B Figure 5. Buffered Output Compare Simplified Block Diagram TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. Overview Pulse-Width Modulation (PWM) Concepts A pulse-width modulated waveform is created when the high to low time ratio, or pulse-width, of a periodic signal can be varied. For example, if the waveform can be incrementally changed by 1/256 of its period, it has 8 bits of resolution. (See Figure 6.) 256 INCREMENTS Freescale Semiconductor, Inc... 1/256 128/256 Figure 6. Pulse-Width Modulation Example As shown in Figure 7, a PWM function has a 16-bit counter, two 16-bit comparators, and an output latch. When the 16-bit counter reaches the modulo value in the 16-bit modulo registers, the 16-bit modulo comparator sets the output latch, indicating a modulo counter overflow. The modulo overflow is used as the reference to start the pulse, thereby setting the period of the waveform. As the counter is incremented, the counter value is compared with the contents of the 16-bit channel register. When a match occurs the latch is reset, ending the pulse. The duty cycle of the signal is varied by changing the value in the 16-bit channel register. TIM08 Reference Manual — Rev. 1.0 30 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Pulse-Width Modulation (PWM) Concepts 16-BIT CHANNEL REGISTER 16-BIT COMPARATOR CHANNEL MATCH CLOCK 16-BIT MODULO COUNTER Freescale Semiconductor, Inc... R LATCH S PWM OUTPUT 16-BIT COMPARATOR MODULO OVERFLOW 16-BIT MODULO REGISTER Figure 7. Pulse-Width Modulation Simplified Block Diagram The input clock frequency to the 16-bit modulo counter, fTCNT, determines the resolution of the PWM signal. The counter clock frequency is determined by the prescaler programming. By increasing the counter clock frequency, the resolution of the PWM signal becomes finer. For example, when using a counter clock of 2 MHz, the resolution of the counter is 500 ns. If fTCNT is changed to 8 MHz, the resolution of the counter increases to 125 ns. The value in the timer modulo registers determines the frequency of the PWM output. For example, the frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the timer modulo registers produces a PWM frequency of fTCNT ÷ 256. The value in the timer channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the timer channel registers produces a duty cycle of 128/256 or 50%. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. Overview The polarity of the pulse can be changed from a logic 1 state to a logic 0 state. Writing to a special control bit is required to obtain a 100% duty cycle (output high all of the time) or a 0% duty cycle (output low all of the time). The PWM output can be used to electronically control the speed of a motor or the position of a servo. The PWM waveform drives an external switching amplifier which in turn controls the speed and direction of the motor. By adding a low-pass filter to a PWM output, the unit can be used as a D/A converter. The longer the high time of the output waveform, the higher the average value of output voltage produced. Other applications include data communication, where the pulse width indicates the data value. Freescale Semiconductor, Inc... Unbuffered PWM Signal Generation Any TIM channel can generate unbuffered PWM signals. The signal is unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the channel registers. An unsynchronized write to the channel registers to change a pulse width could cause incorrect operation for up to two counter periods. For example, if a new pulse width value is written to the channel registers before the previous pulse width match occurred, but after the counter had reached the new value, no pulse width match would occur during that counter period. Or if a new, small value is written during a timer overflow interrupt routine, but the pulse width match is missed because the new value is not written until after the timer counter is past that value, no pulse width match would occur during that counter period. The PWM interrupt occurs at the end of the current pulse. The timer overflow interrupt, by contrast, occurs at the end of the current period. In applications which cannot tolerate erroneous data during output compare pulse width changes, two methods are used to synchronize an unbuffered PWM pulse width. When changing to a longer pulse width, enable timer overflow interrupts and writes the new pulse width during the timer overflow interrupt routine. When changing to a shorter pulse width, enable PWM interrupts and writes the new pulse width value during the PWM interrupt routine. TIM08 Reference Manual — Rev. 1.0 32 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Overview Pulse-Width Modulation (PWM) Concepts Buffered PWM Signal Generation A buffered PWM function eliminates the synchronization problem inherent in the unbuffered PWM by providing two channel registers in which to store pulse width values. In this method, the current pulse width value is contained in the first channel register, while a new pulse width value is written into the second channel register. On counter overflow, the second channel register value is used to generate the pulse width match. By writing new pulse width values only to the unused channel register, erroneous waveforms can be eliminated. Two TIM channels can be linked to form one buffered PWM channel. When the contents of channel register A match the value of the counters, the comparator sets a PWM flag. Channel register A is used as the pulse width value until a new value is written to channel register B. At the next counter overflow, control switches from channel register A to channel register B. Control continues to switch between channel registers A and B as a new value is written to each register. All control functions and output occurs on channel A. The channel B control register is unused, and output pin B reverts to port control. (See Figure 5.) Freescale Semiconductor, Inc... NOTE: In buffered PWM mode, do not write new compare values to the currently active channel registers. The software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Overview For More Information On This Product, Go to: www.freescale.com 33 Freescale Semiconductor, Inc. Overview 16-BIT CHANNEL REGISTER A 16-BIT CHANNEL REGISTER B 16-BIT COMPARATOR A MATCH A MATCH B 16-BIT COMPARATOR B SELECT Freescale Semiconductor, Inc... CLOCK 16-BIT MODULO COUNTER CHANNEL MATCH R LATCH PWM OUTPUT S 16-BIT COMPARATOR MODULO OVERFLOW 16-BIT MODULO REGISTER Figure 8. Buffered PWM Simplified Block Diagram TIM08 Reference Manual — Rev. 1.0 34 Overview For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal Description Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Freescale Semiconductor, Inc... Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Input Capture/Output Compare Pins (TCH0, TCH1, TCH2, TCH3) . .36 Input Capture Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Output Compare Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PWM Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Auxiliary Timer Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . .38 Introduction The TIM has five signal pins that provide connections to the internal functions of the module. These pins are shared with port pins on the microcontroller. This section contains brief descriptions of the TIM input and output signals in their functional groups. See Electrical Specifications for timing information for these signals. NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Signal Description For More Information On This Product, Go to: www.freescale.com 35 Freescale Semiconductor, Inc. Signal Description Signal Groups The block diagram in Figure 9 shows the signal pins. When the pins are not needed for their TIM function, they can be used for general-purpose input or output as part of a parallel data port. The port pins are part of a separate module. Refer to the applicable technical data book for information on the port module associated with the TIM. The block diagram also shows which TIM signals are bidirectional and which are either input or output only. Freescale Semiconductor, Inc... EXTERNAL MCU BUS PORT PIN PORT PIN PORT PIN PORT PIN INTERNAL MCU BUS TCH0 TCH1 TCH2 TCH3 CAPTURE/COMPARE UNIT 16-BIT COUNTER PORT PIN TCLK PRESCALER Figure 9. Function Signal Groups Input Capture/Output Compare Pins (TCH0, TCH1, TCH2, TCH3) Each of these pins is dedicated to one of the timer channels. These pins can be configured for an input capture, output compare, or PWM function. Each channel pin has one 16-bit register, which is used for holding either the input capture value or the output compare/PWM match value. When used as an input, the signal is conditioned so that any pulse longer than one bus clock period is guaranteed to pass. If this pin is not needed for either the input capture, output compare, or PWM function, it can be used for general-purpose I/O. TIM08 Reference Manual — Rev. 1.0 36 Signal Description For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Signal Description Input Capture/Output Compare Pins (TCH0, TCH1, TCH2, TCH3) Input Capture Pins With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the timer counter into the channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate CPU interrupts or DMA service requests on microcontrollers with a DMA module. See Input Capture (IC) Functions for information on the operation of this function. Freescale Semiconductor, Inc... Output Compare Pins With the output compare function, the TIM can generate an output signal at programmable intervals. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate CPU interrupts or DMA service requests on microcontrollers with a DMA module. See Unbuffered Output Compare (OC) Functions and Buffered Output Compare (OC) Functions for information on the operation of these functions. PWM Output Pins With the PWM function, the TIM can generate a pulse-width modulated output signal. When the counter reaches the value in the registers of a PWM channel, the TIM can set, clear, or toggle the channel pin. A PWM function can generate CPU interrupts or DMA service requests on microcontrollers with a DMA module. See Unbuffered Pulse Width Modulation (PWM) Functions and Buffered Pulse Width Modulation (PWM) Functions for information on the operation of these functions. General-Purpose I/O If not used as input capture, output compare, or PWM functions, these pins may be used as general-purpose I/O. This is accomplished by clearing the ELSxB and ELSxA bits in the TSCx register for each channel pin, as described in Capture/Compare Unit. Refer to the applicable technical data book for more information about using these pins as bidirectional I/O pins. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Signal Description For More Information On This Product, Go to: www.freescale.com 37 Freescale Semiconductor, Inc. Signal Description Auxiliary Timer Clock Input (TCLK) TCLK is an external clock input that can be used as the clock source for the timer counter instead of the prescaled bus clock. Any TCLK pulse longer than one bus clock period is guaranteed to pass. See Prescaler for additional information on TCLK. If this pin is not used as a clock input, it can be used as a generalpurpose I/O pin. See Table 1 for information on selecting the function of this pin. The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 + tsu bus frequency The maximum TCLK frequency is: bus frequency 2 PTE3/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the PTE3/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE3 bit in data direction register E. Freescale Semiconductor, Inc... 38 TIM08 Reference Manual — Rev. 1.0 Signal Description For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Prescaler Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Freescale Semiconductor, Inc... Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Timer Status and Control Register (TSC) . . . . . . . . . . . . . . . . . . . . . .41 Introduction The TIM has its own 16-bit counter as the main timing component. This counter clock is derived from the prescaler or the external input pin TCLK. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Prescaler For More Information On This Product, Go to: www.freescale.com 39 Freescale Semiconductor, Inc. Prescaler Prescaler The prescaler generates six clock rates from the bus clock. The prescaler select bits, PS2:PS0, in the timer status and control register (TSC) select the bus clock, a prescaler divider tap, or the external clock, TCLK, as the input to the 16-bit counter. Figure 10 shows the block diagram of the prescaler. BUS CLOCK (IT12) Freescale Semiconductor, Inc... PRESCALER DIVIDER ÷64 ÷32 ÷16 ÷8 ÷4 ÷2 ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 EXT. TCLK PIN SYNCHRONIZER AND DIGITAL FILTER PS2 PS1 PS0 SELECT TO 16-BIT COUNTER Figure 10. Prescaler Block Diagram The bus clock is divided by a six-stage divider chain that provides outputs of the bus clock divided by 2, 4, 8, 16, 32, and 64. The outputs of the divider provide six inputs to a multiplexer (mux) which selects the clock input for the 16-bit counter. The remaining inputs to the mux are the bus clock and a synchronized external input from the TCLK pin. The mux provides one of the eight inputs to the 16-bit counter. The output of the mux is controlled by PS2:PS0 in the timer status and control register. TIM08 Reference Manual — Rev. 1.0 40 Prescaler For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Prescaler Timer Status and Control Register TCLK is an external clock input. TCLK can be used as the clock source for the 16-bit counter instead of the bus clock or its derivative. Figure 11 shows the timing of TCLK and its synchronization to the bus clock. ONE BUS CLOCK IT12 — BUS CLOCK TCLK ⇓ ⇑ ⇑ ⇓ ⇑ Freescale Semiconductor, Inc... COUNTER CLOCK Figure 11. TCLK Timing where tcyc 1 = bus frequency + tsu Timer Status and Control Register TSC Read: Write: Reset: Bit 7 TOF 0 0 6 TOE 0 5 TSTOP 1 4 0 TRST 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0 0 Shading indicates this bit is not used in the prescaler section. Figure 12. Timer Status and Control Register (TSC) TOF — Unused in prescaler; see Timer Status and Control Register for description. TOE — Unused in prescaler; see Timer Status and Control Register for description. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Prescaler For More Information On This Product, Go to: www.freescale.com 41 Freescale Semiconductor, Inc. Prescaler COUNTER CLOCK = BUS CLOCK (IT12) IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE TSTOP COUNTER CLOCK TCNTH:L (PS2:PS0=000) 0000 0001 0002 0003 0004 WRITE TSTOP = 1 W§ W‡ R‡ W‡ W† R† W† * R§ W§ Freescale Semiconductor, Inc... WRITE TSTOP = 0 COUNTER CLOCK = IT12 ÷ 4 IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE TSTOP W‡ W† W‡ W† * * W‡ W‡ COUNTER CLOCK TCNTH:L 0000 WRITE TSTOP = 0 0001 0002 WRITE TSTOP = 1 READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R† READ DATA R§ READ R‡ READ ADDRESS W† WRITE DATA W§ WRITE W‡ WRITE ADDRESS * Figure 13. TSTOP Timing TIM08 Reference Manual — Rev. 1.0 42 Prescaler For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Prescaler Timer Status and Control Register TSTOP — Timer stop This read/write bit stops the timer counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the timer counter until the TIM is enabled. 1 = Timer counter stopped 0 = Timer counter active To preserve the correct timing relationship, TSTOP stops the input clock to the prescaler. The relationship cannot be preserved when using the external TCLK as the counter clock. Figure 13 for details on the timing of the TSTOP function. TRST — Timer reset Setting this write-only bit resets the timer counter and the timer prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the timer counter is reset, and always reads 0. Reset clears the TRST bit. 1 = Prescaler and timer counter cleared 0 = No effect See Figure 14 for details on the timing of the TRST function. Freescale Semiconductor, Inc... NOTE: Setting the TSTOP and TRST bits simultaneously stops the timer counter at a value of $0000. Bit 3 — Not used; always reads 0. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Prescaler For More Information On This Product, Go to: www.freescale.com 43 Freescale Semiconductor, Inc. Prescaler COUNTER CLOCK = BUS CLOCK (IT12) IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK W‡ W† W§ Freescale Semiconductor, Inc... (PS2:PS0=000) TCNTH:L 0014 0015 0000 0001 0002 0003 WRITE TRST = 1 COUNTER CLOCK = IT12 ÷ 4 IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK TCNTH:L 0004 0005 0006 0000 WRITE TRST = 1 READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R† READ DATA R§ READ R‡ READ ADDRESS W† WRITE DATA W§ WRITE W‡ WRITE ADDRESS 0001 W‡ W† W§ * Figure 14. TRST Timing TIM08 Reference Manual — Rev. 1.0 44 Prescaler For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Prescaler Timer Status and Control Register PS2:PS0 — Prescaler bits These read/write bits select the bus clock, one of the six prescaler outputs, or the TCLK pin as the input to the timer counter. Table 1 shows the prescaler selection encoding, including the TIM clock source, and the function of the TCLK pin. Reset clears the PS2:PS0 bits. Table 1. Prescaler Selection PS2:1:0 TIM Clock Source Bus Clock Bus Clock ÷ 2 Bus Clock ÷ 4 Bus Clock ÷ 8 Bus Clock ÷ 16 Bus Clock ÷ 32 Bus Clock ÷ 64 TCLK Freescale Semiconductor, Inc... PORT/TCLK Function PORT PORT PORT PORT PORT PORT PORT TCLK 000 001 010 011 100 101 110 111 NOTE: NOTE: Stop the TIM before changing the prescaler output. Before writing to the prescaler select bits (PS2:PS0), set the timer stop bit (TSTOP). Changing the prescaler control bits while the TIM is running may cause an extra count if the input clock previously selected was a logic level 0 and the new input clock logic level is 1. Refer to Stop Mode for information on stopping the prescaler. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Prescaler For More Information On This Product, Go to: www.freescale.com 45 Freescale Semiconductor, Inc. Prescaler Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 46 Prescaler For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 16-Bit Modulo Counter Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Freescale Semiconductor, Inc... Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Timer Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Introduction The timer counter provides the capture/compare units with a counter reference for the input capture (IC) functions, the output compare (OC) functions, and the pulse-width modulation (PWM) functions. Timer Counter The timer counter (TCNT) is the key timing component for the capture/compare unit. The timer counter is a 16-bit modulo counter with a programmable input clock and the capability to be stopped or reset by manipulating control bits in the timer status and control register. The 16-bit modulo counter consists of a 16-bit counter, a 16-bit comparator, a 16-bit modulo register, and interrupt generation logic. Refer to Figure 15. TIM08 Reference Manual — Rev. 1.0 MOTOROLA 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com 47 Freescale Semiconductor, Inc. 16-Bit Modulo COUNTER CLOCK (FROM PRESCALER) 16-BIT MODULO COUNTER TCNTH:TCNTL TO CAPTURE/ COMPARE UNIT 16-BIT COMPARATOR COUNTER OVERFLOW Freescale Semiconductor, Inc... 16-BIT MODULO REGISTER TMODH:TMODL Figure 15. 16-Bit Modulo Counter Simplified Block Diagram After reset, the TIM counter is stopped, and the bus clock is selected as the input to the counter. User software can configure the system to use the bus clock, one of six outputs from the prescaler, or an external clock through the TCLK input pin. See Prescaler for more details on prescaler operation and input clock selection. After clearing the TSTOP bit in the timer status and control (TSC) register, the counter begins counting from $0000. When the contents of the modulo register (TMOD) match the value of the counter (TCNT), the comparator sets the timer overflow flag (TOF) in the TSC register. Other events can occur when the flag is set. An interrupt can be generated if enabled, and state changes can occur on pins associated with PWM functions in the capture/compare unit. An interrupt is generated on a timer overflow if the interrupt enable bit, TOE, is set in the TSC register. See CPU Interrupts for information on interrupt operation and DMA Service Requests for information on service request operation. A PWM output pin can be toggled on a counter overflow. See Unbuffered Pulse Width Modulation (PWM) Functions and Buffered Pulse Width Modulation (PWM) Functions for more information on using this function. TIM08 Reference Manual — Rev. 1.0 48 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 16-Bit Modulo Counter Timer Status and Control Register Timer Status and Control Register TSC Read: Write: Reset: Bit 7 TOF 0 0 6 TOE 0 5 TSTOP 1 4 0 TRST 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0 0 Shading indicates this bit is not used in the counter section. Freescale Semiconductor, Inc... Figure 16. Timer Status and Control Register (TSC) TOF — Timer Overflow Flag This clearable flag is set when the timer counter reaches the modulo value programmed in the timer modulo registers. Clear TOF by reading the timer status and control register when TOF is set and then writing a 0 to TOF. If another timer overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to this bit has no effect. Reset clears the TOF bit. 1 = Timer counter has reached modulo value. 0 = Timer counter has not reached modulo value. TOE — Timer Overflow Enable This read/write bit enables timer overflow interrupts when the TOF bit becomes set. Reset clears the TOE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled TSTOP — Timer STOP This read/write bit stops the timer counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the timer counter until the TIM is enabled. 1 = Timer counter stopped 0 = Timer counter active To preserve the correct timing relationship, TSTOP stops the input clock to the prescaler. The relationship cannot be preserved when TIM08 Reference Manual — Rev. 1.0 MOTOROLA 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com 49 Freescale Semiconductor, Inc. 16-Bit Modulo using the external TCLK as the counter clock. Refer to Figure 17 for details on the timing of the TSTOP function. NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. COUNTER CLOCK = BUS CLOCK (IT12) IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE TSTOP COUNTER CLOCK TCNTH:L (PS2:PS0=000) 0000 0001 0002 0003 0004 WRITE TSTOP = 1 W§ Freescale Semiconductor, Inc... W‡ R‡ W‡ W† R† W† * R§ W§ WRITE TSTOP = 0 COUNTER CLOCK = IT12 ÷ 4 IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE TSTOP W‡ W† W‡ W† * * W‡ W‡ COUNTER CLOCK TCNTH:L 0000 WRITE TSTOP = 0 0001 0002 WRITE TSTOP = 1 READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R† READ DATA R§ READ R‡ READ ADDRESS W† WRITE DATA W§ WRITE W‡ WRITE ADDRESS * Figure 17. TSTOP Timing TIM08 Reference Manual — Rev. 1.0 50 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 16-Bit Modulo Counter Timer Status and Control Register TRST — Timer reset Setting this write-only bit resets the timer counter and the timer prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the timer counter is reset, and always reads 0. Reset clears the TRST bit. 1 = Prescaler and timer counter cleared 0 = No effect See Figure 18 for details on the timing of the TRST function. Freescale Semiconductor, Inc... NOTE: Setting the TSTOP and TRST bits simultaneously stops the timer counter at a value of $0000. PS2:PS0 — Unused in counter; see Timer Status and Control Register for a description. TIM08 Reference Manual — Rev. 1.0 MOTOROLA 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com 51 Freescale Semiconductor, Inc. 16-Bit Modulo COUNTER CLOCK = BUS CLOCK (IT12) IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK W‡ W† W§ Freescale Semiconductor, Inc... (PS2:PS0=000) TCNTH:L 0014 0015 0000 0001 0002 0003 WRITE TRST = 1 COUNTER CLOCK = IT12 ÷ 4 IT12 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK TCNTH:L 0004 0005 0006 0000 WRITE TRST = 1 READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R† READ DATA R§ READ R‡ READ ADDRESS W† WRITE DATA W§ WRITE W‡ WRITE ADDRESS 0001 W‡ W† W§ * Figure 18. TRST Timing TIM08 Reference Manual — Rev. 1.0 52 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. 16-Bit Modulo Counter Timer Counter Registers Timer Counter Registers These two read-only timer counter registers, TCNTH and TCNTL, contain the high and low bytes of the value in the timer counter. The counter value can be read at any time with user software without affecting its value. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL). Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. The LDHX instruction can be used to read a value from TCNT. The counter is set to $0000 on reset or when the timer reset bit (TRST) is set. Freescale Semiconductor, Inc... TCNTH Read: Write: Reset: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 0 0 0 0 0 0 0 0 TCNTL Read: Write: Reset: Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 0 0 0 0 0 0 0 0 Figure 19. Timer Counter Registers (TCNTH:TCNTL) TIM08 Reference Manual — Rev. 1.0 MOTOROLA 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com 53 Freescale Semiconductor, Inc. 16-Bit Modulo Timer Counter Modulo Registers These two read/write timer counter modulo registers, TMODH and TMODL, contain the high and low bytes of the modulo value for the timer counter. When the timer counter reaches the modulo value, the TOF flag is automatically set by hardware, and the timer counter resumes counting from $0000 at the next clock. The overflow flag (TOF) and overflow interrupts are inhibited after a write to the high byte (TMODH) until the low byte (TMODL) is written. The STHX instruction can be used to write values to TMOD, and the LDHX instruction can be used to read values from TMOD. Reset sets the timer counter modulo registers to $FFFF, enabling the modulo counter to act as a free-running counter. Freescale Semiconductor, Inc... TMODH Read: Write: Reset: Bit 15 Bit 15 1 14 14 1 13 13 1 12 12 1 11 11 1 10 10 1 9 9 1 Bit 8 Bit 8 1 TMODL Read: Write: Reset: Bit 7 Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1 Figure 20. Timer Counter Modulo Registers (TMODH:TMODL) NOTE: NOTE: If TMODH:TMODL is set to $0000, a TOF is generated on the first cycle in which the match occurs, but not subsequently. Stop and reset the timer counter before writing to the timer counter modulo registers. TIM08 Reference Manual — Rev. 1.0 54 16-Bit Modulo Counter For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Freescale Semiconductor, Inc... Input Capture (IC) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .60 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Unbuffered Output Compare (OC) Functions . . . . . . . . . . . . . . . . . . .65 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .67 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Buffered Output Compare (OC) Functions . . . . . . . . . . . . . . . . . . . . .72 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . . . . .75 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Unbuffered Pulse Width Modulation (PWM) Functions . . . . . . . . . . .80 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .83 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Buffered Pulse Width Modulation (PWM) Functions . . . . . . . . . . . . .90 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . .94 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 55 Freescale Semiconductor, Inc. Capture/Compare Unit Introduction The capture/compare unit is one of the major submodules of the TIM. It contains the input capture (IC) functions, the output compare (OC) functions, and the pulse-width modulation (PWM) functions. The function provided by each of the channels is determined by the configuration of the status and control register for each channel. The following sections describe how to set up the status and control registers to generate IC functions, unbuffered and buffered OC functions, and unbuffered and buffered PWM functions. See Input Capture (IC) Concepts, Output Compare (OC) Concepts, and Pulse-Width Modulation (PWM) Concepts for more information about these functions. Freescale Semiconductor, Inc... NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 56 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Input Capture (IC) Functions Input Capture (IC) Functions Each TIM input capture pin TCH0–TCH3, when used as an input capture function, has a 16-bit register latch (TCHxH/L), input edge-detection/selection logic, and interrupt synchronization/generation logic. All of the input capture functions use the same 16-bit timer counter (TCNT). The latch captures the contents of the TCNT when the selected event occurs at the corresponding input capture pin. Freescale Semiconductor, Inc... See Input Capture (IC) Concepts for additional information on the basic operation of an input capture function. The edge detection logic contains control bits that allow user software to select the edge polarity to be recognized. These are the ELSxB and ELSxA bits in the timer status and control register (TSCx). Each of the input capture functions can be independently configured to detect rising edges only, falling edges only, any edge (rising or falling), or disable the input capture function. Table 2 for the required bit patterns. The input capture functions operate independently of each other and can capture the same TCNT value if the input edges are all detected within the same timer count cycle. The interrupt generation logic includes a status flag, which indicates that an edge is detected, and a local interrupt enable bit, which determines if the corresponding input capture function will generate an interrupt or service request. The input capture sets the CHxF bit in the TSCx and can cause an interrupt or service request if the corresponding CHxIE bit is set in the TSCx. If the interrupt is disabled (CHxIE = 0), the input capture is operating in polled mode where software must read the status flag to recognize that an edge was detected. Refer to CPU Interrupts for additional details on interrupt operation and DMA Service Requests for additional details on service request operation. Because input capture events are generally asynchronous to the timer counter, they are synchronized to the bus clock so that actual latching of the TCNT contents occurs just after the counter increments. The input is conditioned in such a way that any event longer than one bus clock is guaranteed to be captured. The relationship of the bus clock to the TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 57 Freescale Semiconductor, Inc. Capture/Compare Unit output of the synchronizer is shown in Figure 21. The value latched into the timer channel register by an input capture corresponds to the value of the counter one bus clock cycle after the input transition that triggered the edge detection logic. There can be up to one bus clock cycle of uncertainty in latching of the input transition. The maximum time is determined by the bus clock frequency, fOP. IT12 Freescale Semiconductor, Inc... IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS COUNTER CLOCK TCNTH:TCNTL 0019 0020 0021 0022 0023 0024 0025 0026 0027 $8c $0c TCH0 PIN CH0F INTERNAL READ/WRITE TCH0H:TCH0L TSC0 0c ← EDGE OCCURRING BEFORE ↓ IT12 IS RECOGNIZED. R * 0022 W * 0c 8c R† READ CH0F = 1 W† WRITE CH0F = 0 NAME IT12, IT23 TCNTH:TCNTL TCH0 pin CH0F TCH0H:TCH0L TSC0 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 input pin CH0F bit in TSC0 register 16-bit value in TCH0 register Timer status and control register, channel 0 Figure 21. Input Capture Timing TIM08 Reference Manual — Rev. 1.0 58 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Input Capture (IC) Functions Input captures are inhibited between reads from TCHxH and TCHxL. The LDHX instruction can be used to read the contents of the timer channel register TCHxH:TCHxL. An input capture occurs every time a selected edge is detected, even if the input capture flag is already set. This means that the value read from the timer channel register corresponds to the most recent edge at the pin, which may not be the edge that caused the input capture flag to be set. Freescale Semiconductor, Inc... If any of the pins TCH0–TCH3 are not needed for an input capture function, they can be used as general-purpose input/output. For more information on general-purpose I/O ports, refer to the applicable technical data book. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 59 Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform input capture functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following in input capture mode: • • Flags input captures Enables input capture interrupts Selects input capture mode of operation Selects rising, falling, or any edge as the active input capture trigger Bit 7 CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0 Freescale Semiconductor, Inc... • • TSC0 Read: Write: Reset: TSC1 Read: Write: Reset: Bit 7 CH1F 0 0 6 CH1IE 0 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0 TSC2 Read: Write: Reset: Bit 7 CH2F 0 0 6 CH2IE 0 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 Bit 0 CH2MAX 0 TSC3 Read: Write: Reset: Bit 7 CH3F 0 0 6 CH3IE 0 5 0 0 4 MS3A 0 3 ELS3B 0 2 ELS3A 0 1 TOV3 0 Bit 0 CH3MAX 0 Shading indicates this bit is not used for input capture functions. Figure 22. Timer Channel Status and Control Registers (TSC0–TSC3) TIM08 Reference Manual — Rev. 1.0 60 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Input Capture (IC) Functions CHxF — Channel x Flag When channel x is an input capture channel, this clearable bit is set when an active edge occurs on the channel x pin. When CPU interrupts are enabled (CHxE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Freescale Semiconductor, Inc... When DMA service requests are available and enabled (CHxE:DMAxS = 1:1), clear CHxF by reading or writing to the low byte of the channel register (TCHxL). Writing a 1 to this bit has no effect. Reset clears the CHxF bit. 1 = Input capture has occurred on channel x. 0 = No input capture has occurred on channel x. CHxIE — Channel x Interrupt Enable This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register selects channel x CPU interrupts or DMA service requests. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode Select bit B This bit should be cleared for input capture mode operation. MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register, and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register, and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 61 Freescale Semiconductor, Inc. Capture/Compare Unit MSxA — Mode Select bit A This bit should be cleared for input capture operation. This read/write bit selects input capture mode or unbuffered OC/PWM mode. MS0A and MS1A are active only when MS0B = 0. MS2A and MS3A are active only when MS2B = 0. Reset clears the MSxA bit. 1 = Unbuffered OC/PWM operation 0 = Input capture operation NOTE: Freescale Semiconductor, Inc... Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/Level Select bits When channel x is an input capture channel, these read/write bits control the active edge sensing logic on channel x. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 2 shows the configuration selected by ELSxB and ELSxA in input capture mode. Reset clears the ELSxB and ELSxA bits. NOTE: Before enabling the channel register for input capture, make sure that the PTE/TCHx pin is stable for a minimum of two bus clocks. Table 2. Input Capture Mode and Edge Selection MSxB: MSxA 00 00 00 00 ELSxB: ELSxA 00 01 10 11 Mode Output preset Input capture Input capture Input capture Configuration TCHx pin under port control; not used in IC mode Capture on rising edge only Capture on falling edge only Capture on rising or falling edge TOVx — Toggle on Overflow This bit is unused for input capture operation. CHxMAX — PWM 100% duty cycle This bit is unused for input capture operation. TIM08 Reference Manual — Rev. 1.0 62 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Input Capture (IC) Functions Timer Channel Registers These read/write registers are used as the 16-bit input capture register latches for input capture functions. These registers latch the value of TCNT when a specified transition is detected on the corresponding input capture pin. The state of these registers is indeterminate after reset. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the channel register (TCHxH) inhibits input captures until the low byte (TCHxL) is read. This prevents another input capture from overwriting the TCHxH:TCHxL registers before the previous value has been read. An overwrite of TCHxH:TCHxL will occur if another IC is received before the TCHxH is read. The LDHX instruction may be used to read these registers. Freescale Semiconductor, Inc... NOTE: Writing to the timer channel registers will overwrite any input capture data. If a timer channel register is not used for an input capture function, it can be used as a storage location. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 63 Freescale Semiconductor, Inc. Capture/Compare Unit TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 10 Bit Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 10 Bit Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 23. Timer Channel Register (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 64 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Output Compare (OC) Functions Unbuffered Output Compare (OC) Functions Each of the TIM output compare pins TCH0–TCH3, when used as an unbuffered output compare function, has a dedicated 16-bit compare register (TCHxH/L), a 16-bit comparator, and interrupt generation logic. The 16-bit modulo counter value, TCNT, is used as the timing reference for all unbuffered output compares. When the programmed contents of a timer channel register match TCNT, the 16-bit comparator generates an output compare match, and certain automatic actions are initiated. These automatic actions can be a hardware interrupt request and state changes at the related timer output pin. See Unbuffered Output Compares for more information on the basic operation of this function. When the output compare match occurs, a status flag CHxF is set in TSCx. Figure 24 shows the timing of CHxF relative to the bus clocks, as well as the timing relationships for state changes described in the following paragraphs. An output compare pin can be programmed to change states when an output compare match occurs. TSCx control bits ELSxA and ELSxB determine the output state of the pin on an output compare match. An output compare channel can be programmed to toggle, clear, or set the TCHx pin on an output compare match. See Table 3 for the control bit configurations to select the state of an output compare pin. If the interrupt enable bit (CHxIE) for this output compare function is set in TSCx, a CPU interrupt or DMA service request is generated on a successful output match. If the interrupt is disabled, CHxF can be polled by software to determine when an output compare match has occurred. See CPU Interrupts for details on interrupt operation and DMA Service Requests for details on service request operation. Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 65 Freescale Semiconductor, Inc. Capture/Compare Unit IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK R‡ R† W‡ W† Freescale Semiconductor, Inc... TCNTH:TCNTL TCH0H:TCH0L CH0F TCH0 pin TSC0 18 0050 0050 0051 0052 0050 0053 0054 0055 0050 0056 { WRITE CH0F = 0 READ CH0F = 1 CLEAR ON OC/PWM 98 18 * READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R‡ READ TSC0 R† READ DATA W† WRITE DATA W‡ WRITE TSC0 NAME IT12, IT23 TCNTH:TCNTL TCH0H:TCH0L CH0F TCH0 pin TSC0 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 data register for output compare value CH0F bit in TSC0 register Timer channel 0 output pin Timer status and control register, channel 0 Figure 24. Unbuffered Output Compare Timing TIM08 Reference Manual — Rev. 1.0 66 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Output Compare (OC) Functions Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform output compare functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following in unbuffered output compare mode: • • Flags output compares Enables output compare interrupts Selects initial level of TCHx output pin Selects unbuffered output compare mode operation Selects high, low, or toggling output on output compare match 7 CH0F CH0IE Write: Reset: TSC1 Read: Write: Reset: TSC2 Read: Write: Reset: TSC3 Read: Write: Reset: 0 0 7 CH1F CH1IE 0 0 7 CH2F CH2IE 0 0 7 CH3F CH3IE 0 0 0 0 0 0 0 0 0 0 MS3A ELS3B ELS3A TOV3 CH3MAX 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... • • • TSC0 Read: Shading indicates this bit is not used for outout compares. Figure 25. Timer Channel Status and Control Registers (TSC0–TSC3) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 67 Freescale Semiconductor, Inc. Capture/Compare Unit CHxF — Channel x Flag When channel x is an output compare channel, CHxF is set when the value in the timer counter registers matches the value in the timer channel x registers. When CPU interrupts are enabled (CHxE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. When DMA service requests are available and enabled (CHxE:DMAxS = 1:1), clear CHxF by reading or writing to the low byte of the channel register (TCHxL). Writing a 1 to this bit has no effect. Reset clears the CHxF bit. 1 = Output compare on channel x 0 = No output compare on channel x CHxIE — Channel x interrupt enable This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register selects channel x CPU interrupts or DMA service requests. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode select bit B This bit should be cleared for unbuffered output compare operation. MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register, and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register, and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled Freescale Semiconductor, Inc... 68 TIM08 Reference Manual — Rev. 1.0 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Output Compare (OC) Functions MSxA — Mode Select bit A This bit has different functions, depending on the state of ELSxB and ELSxA. When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. To select the level of your initial output, write the appropriate value to MSxA while ELSxB:A = 00. Then configure all bits in the TSCx as required for your application. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... When ELSxB:A ≠ 00, this read/write bit selects input capture mode or unbuffered OC/PWM mode. This bit should be set for unbuffered output compare operation. MS0A and MS1A are active only when MS0B = 0. MS2A and MS3A are active only when MS2B = 0. Reset clears the MSxA bit. 1 = Unbuffered OC/PWM operation 0 = Input capture operation NOTE: Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/Level Select bits When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 3 shows the configuration selected by ELSxB and ELSxA in unbuffered output compare mode. Reset clears the ELSxB and ELSxA bits. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 69 Freescale Semiconductor, Inc. Capture/Compare Unit Table 3. Unbuffered Output Compare Mode and Level Selection MSxB: MSxA X0 X1 01 01 01 01 ELSxB: ELSxA 00 00 00 01 10 11 Mode Output preset Output preset Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Configuration Set initial output level high Set initial output level low TCHx pin under port control; set initial output level low. Toggle output on OC match Clear output on OC match Set output on OC match Freescale Semiconductor, Inc... TOVx — Toggle on Overflow This bit should be cleared for unbuffered output compare operation. NOTE: Although not typically used for output compare functions, this bit is active and will affect the operation of the TIM in output compare mode. Refer to Timer Channel Status and Control Registers. CHxMAX — PWM 100% duty cycle This bit should be cleared for unbuffered output compare operation. NOTE: Although not typically used for output compare functions, this bit is active and will affect the operation of the TIM in output compare mode. Refer to Timer Channel Status and Control Registers. Timer Channel Registers These read/write registers are used as the 16-bit compare register for output compare functions. These registers contain the output compare value for the output compare function. The state of the channel registers after reset is unknown. In unbuffered output compare mode (MSxB:MSxA = 0:1), output compares are inhibited between writes to TCHxH and TCHxL. This prevents another output compare from occurring until the new output compare value is written. The STHX instruction can be used to write to TCHxH:TCHxL. If a timer channel register is not used for an output compare function, it can be used as a storage location. TIM08 Reference Manual — Rev. 1.0 70 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Output Compare (OC) Functions TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 10 Bit Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 26. Timer Channel Registers (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 71 Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Output Compare (OC) Functions TIM output compare pins TCH0 and TCH2 may be used as buffered output compare functions. This is accomplished by linking two unbuffered output compare channels together to form one buffered output compare channel. When used as buffered output compare pins, TCH0 and TCH2 have two dedicated 16-bit compare registers (TCHxH/L), two 16-bit comparators, and interrupt generation logic. The 16-bit modulo counter value, TCNT, is used as the timing reference for all unbuffered PWM functions. When the programmed contents of the active timer channel register matches TCNT, the active 16-bit comparator generates an output compare match, and certain automatic actions are initiated for that output compare function. These automatic actions can be a hardware interrupt request and state changes at the related timer output pin. See Buffered Output Compares for information on the basic operation of this function. When the output compare match occurs, a status flag CHxF is set in TSCx. Figure 27 shows the timing of CHxF relative to the bus clocks, as well as the timing relationships for state changes described in the following paragraphs. An output compare pin can be programmed to change states when an output compare match occurs. TSCx control bits ELSxA and ELSxB determine the output state of the pin on an output compare match. An output compare channel can be programmed to toggle, clear, or set the TCHx pin on an output compare match. See Table 4 for the control bit configurations to select the state of an output compare pin. If the interrupt enable bit (CHxIE) for this output compare function is set in TSCx, a CPU interrupt is generated on a successful output match. If the interrupt is disabled, CHxF can be polled by software to determine when an output compare match has occurred. See CPU Interrupts for details on interrupt operation. Freescale Semiconductor, Inc... NOTE: DMA service requests are not available in buffered output compare mode. TIM08 Reference Manual — Rev. 1.0 72 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Output Compare (OC) Functions To use TCH0 as a buffered output compare pin, set the MS0B bit in TSC0. This will disable TCH1 as a TIM pin, and it will revert to port control. TSC0 controls and monitors the buffered output compare function, and TSC1 is unused. The channel 0 registers, TCH0H:TCH0L, initially control the output compare value on the TCH0 pin. Writing to the channel 1 registers enables the channel 1 registers to synchronously control the output compare value at the beginning of the next counter period. At each subsequent overflow, the channel registers (0 or 1) last written to control the output compare value. See Figure 27. Freescale Semiconductor, Inc... To use TCH2 as a buffered output compare pin, set the MS2B bit in TSC2. This will disable TCH3 as a TIM pin, and it will revert to port control. TSC2 controls and monitors the buffered output compare function, and TSC3 is unused. The channel 2 registers, TCH2H:TCH2L, initially control the output compare value on the TCH2 pin. Writing to the channel 3 registers enables the channel 3 registers to synchronously control the output compare value at the beginning of the next PWM period. At each subsequent overflow, the channel registers (2 or 3) last written to control the output compare value. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 73 Freescale Semiconductor, Inc. Capture/Compare Unit IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK TCNT 0050 0056 0050 0051 0052 0053 0054 0056 0050 0055 0056 0000 0001 0056 0050 R‡ R† W‡ W† W§ W† Freescale Semiconductor, Inc... TMODH:TMODL TCH0H:TCH0L CH0F TCH1H:TCH1L TCH0 pin TSC0 24 { WRITE CH0F = 0 0040 0001 TOGGLE ON OC 24 R‡ READ TSC0 W‡ WRITE TSC0 W§ WRITE TCH1L a4 READ CH0F = 1 0040 TOGGLE ON OC a4 R† READ DATA W† WRITE DATA NAME IT12, IT23 TCNTH:TCNTL TCH0H:TCH0L CH0F TCH1H:TCH1L TCH0 pin TSC0 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 data register for output compare value CH0F bit in TSC0 register Timer channel 1 data register for output compare value Timer channel 0 output pin Timer status and control register, channel 0 Figure 27. Buffered Output Compare Timing NOTE: In buffered output compare mode, do not write new compare values to the currently active channel registers. The software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compare signals. TIM08 Reference Manual — Rev. 1.0 74 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Status and Control Registers Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform output compare functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following in buffered output compare mode: Freescale Semiconductor, Inc... • • • • • TSC0 Read: Write: Flags output compares Enables output compare interrupts Selects initial level of TCHx output pin Selects buffered output compare mode of operation Selects high, low, or toggling output on output compare match Bit 7 CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0 Reset: TSC2 Read: Write: Reset: Bit 7 CH2F 6 CH2IE 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 Bit 0 CH2MAX 0 0 0 0 Shading indicates this bit is not used for output compares. Figure 28. Timer Channel Status and Control Register (TSC0 and TSC2) CHxF — Channel x flag When channel x is a buffered output compare channel, CHxF is set when the value in the timer counter registers matches the value in the timer channel x registers. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 75 Freescale Semiconductor, Inc. Capture/Compare Unit When CPU interrupts are enabled (CHxE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. DMA service requests may not be used with buffered output compare functions. Freescale Semiconductor, Inc... Writing a 1 to this bit has no effect. Reset clears the CHxF bit. 1 = Output compare on channel x 0 = No output compare on channel x CHxIE — Channel x interrupt enable This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register should be cleared to select channel x CPU interrupts. DMA service requests cannot be used with buffered OC mode. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode select bit B This bit should be set for buffered OC operation. MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register, and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register, and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled MSxA — Mode select bit A This bit has different functions, depending on the state of ELSxB and ELSxA. TIM08 Reference Manual — Rev. 1.0 76 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Status and Control Registers When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. To select the level of your initial output, write the appropriate value to MSxA while ELSxB:A = 00. Then configure all bits in the TSCx as required for your application. 1 = Initial output level low 0 = Initial output level high When ELSxB:A ≠ 00, this bit is unused for buffered OC operation. NOTE: Freescale Semiconductor, Inc... Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/level select bits When channel x is a buffered output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 4 shows the configuration selected by ELSxB and ELSxA in buffered output compare mode. Reset clears the ELSxB and ELSxA bits. Table 4. Buffered Output Compare Mode and Level Selection MSxB: MSxA X0 X1 1X 1X 1X 1X ELSxB: ELSxA 00 00 00 01 10 11 Mode Output preset Output preset Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Configuration Set initial output level high Set initial output level low TCHx pin under port control; set initial output level. Toggle output on OC match Clear output on OC match Set output on OC match TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 77 Freescale Semiconductor, Inc. Capture/Compare Unit TOVx — Toggle on overflow This bit should be cleared for buffered output compare operation. NOTE: Although not typically used for output compare functions, this bit is active and will affect the operation of the TIM in output compare mode. See Timer Channel Status and Control Registers. CHxMAX — PWM 100% duty cycle Freescale Semiconductor, Inc... This bit should be cleared for buffered output compare operation. NOTE: Although not typically used for output compare functions, this bit is active and will affect the operation of the TIM in output compare mode. See Timer Channel Status and Control Registers. Timer Channel Registers These read/write registers are used as the 16-bit compare register for output compare functions. These registers contain the output compare value for the output compare function. The state of the channel registers after reset is unknown. In buffered output compare mode (MSxB = 1), output compares are inhibited between writes to TCHxH and TCHxL of the active channel. This prevents another output compare from occurring until the new output compare value is written. Output compares are allowed between writes to TCHxH and TCHxL of the inactive channel. The STHX instruction can be used to write to TCHxH:L. If a timer channel register is not used for an output compare function, it can be used as a storage location. TIM08 Reference Manual — Rev. 1.0 78 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Status and Control Registers TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 29. Timer Channel Registers (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 79 Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions Each of the TIM output compare pins TCH0–TCH3, when used as an unbuffered PWM function, has a dedicated 16-bit compare register (TCHxH/L), a 16-bit comparator, and interrupt generation logic. The 16-bit modulo counter value, TCNT, is used as the timing reference for all unbuffered PWM functions. When the programmed contents of a timer channel register match TCNT, the 16-bit comparator generates a PWM match, and certain automatic actions are initiated. These automatic actions can be a hardware interrupt request and state changes at the related timer output pin. When generating an unbuffered PWM signal, the value in the timer channel registers determines the pulse width of the PWM signal, and the value of the timer modulo registers determines the period of the PWM signal. Refer to Figure 30. The toggle on overflow feature links the overflow of the 16-bit modulo counter to the unbuffered PWM channel. See Pulse-Width Modulation (PWM) Concepts and Unbuffered PWM Signal Generation for more information on the basic operation of this function. Freescale Semiconductor, Inc... PERIOD TIMER OVERFLOW PULSE WIDTH TCHx OUTPUT COMPARE Figure 30. PWM Period and Pulse Width TIM08 Reference Manual — Rev. 1.0 80 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions When the PWM match occurs, a status flag CHxF is set in TSCx. Figure 31 shows the timing of CHxF relative to the bus clocks, as well as the timing relationships for state changes and interrupts described in the following paragraphs. A PWM pin can be programmed to change states when a PWM match occurs, thereby determining the pulse width of the PWM signal. TSCx control bits ELSxA and ELSxB determine the output state of the pin on a PWM match. An unbuffered PWM channel can be programmed to toggle, clear, or set the TCHx pin on a PWM match. Table 5 for the control bit configurations to select the state of a PWM signal pin. If the interrupt enable bit (CHxIE) for this PWM function is set in TSCx, a CPU interrupt or DMA service request is generated on a PWM match. If the interrupt is disabled, CHxF can be polled by software to determine when a match has occurred. See CPU Interrupts for details on interrupt operation and See DMA Service Requests for details on service request operation. To generate a signal with 100% duty cycle, use the CHxMAX bit in the TSCx. To generate a signal with 0% duty cycle, program the PWM channel to either set or clear (not toggle) on PWM match, then clear the TOVx bit to start a 0% duty cycle signal. Freescale Semiconductor, Inc... NOTE: In PWM signal generation, do not program the PWM channel to toggle on PWM match. Toggling on PWM match prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on PWM match can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. TIM08 Reference Manual Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 81 Freescale Semiconductor, Inc. Capture/Compare Unit IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK TCNTH:TCNTL TCH0H:TCH0L CH0F TMODH:TMODL TOF TCH0 PIN TSC0 TSC 1A 00 TOGGLE ON OVERFLOW CLEAR ON PWM MATCH 9A 1A 80 0055 0050 0050 0051 0052 0050 0053 0054 0055 0050 WRITE CH0F = 0 0055 0055 0000 0001 R‡ R† W‡ W† Freescale Semiconductor, Inc... READ CH0F = 1 * READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R‡ READ TSC0 R† READ DATA W† WRITE DATA W‡ WRITE TSC0 NAME IT12, IT23 TCNTH:TCNTL TCH0H:TCH0L CH0F TMODH:TMODL TOF TCH0 pin TSC0 TSC { DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 data register for output compare value CH0F bit in TSC0 register Timer counter modulo register Timer counter overflow flag (TOF) bit in TSC register Timer channel 0 output pin Timer status and control register, channel 0 Timer status and control register Figure 31. Unbuffered PWM Timing TIM08 Reference Manual — Rev. 1.0 82 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform PWM functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following in unbuffered PWM mode: • • • Flags pulse width matches Enables PWM interrupts Selects initial level of TCHx output pin Selects unbuffered PWM operation Selects high, low, or toggling output on PWM match Selects output toggling on timer overflow Selects 100% PWM duty cycle Freescale Semiconductor, Inc... • • • • TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 83 Freescale Semiconductor, Inc. Capture/Compare Unit TSC0 Read: Write: Reset: Bit 7 CH0F 6 CH0IE 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0 0 0 0 TSC1 Read: Write: Bit 7 CH1F 6 CH1IE 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 0 CH1MAX 0 0 0 0 Freescale Semiconductor, Inc... Reset: TSC2 Read: Write: Reset: Bit 7 CH2F 6 CH2IE 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 0 CH2MAX 0 0 0 0 TSC3 Read: Write: Reset: Bit 7 CH3F 6 CH3IE 5 0 0 4 MS3A 0 3 ELS3B 0 2 ELS3A 0 1 TOV3 0 Bit 0 CH3MAX 0 0 0 0 Figure 32. Timer Channel Status and Control Registers (TSC0–TSC3) CHxF — Channel x flag When channel x is a PWM channel, CHxF is set when the value in the timer counter registers matches the value in the timer channel x registers. When CPU interrupts are enabled (CHxE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. TIM08 Reference Manual — Rev. 1.0 84 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions When DMA service requests are available and enabled (CHxE:DMAxS = 1:1), clear CHxF by reading or writing to the low byte of the channel register (TCHxL). Writing a 1 to this bit has no effect. Reset clears the CHxF bit. 1 = PWM match on channel x 0 = No PWM match on channel x CHxIE — Channel x interrupt enable This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register selects channel x CPU interrupts or DMA service requests. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode select bit B This bit should be cleared for unbuffered PWM operation. MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled MSxA — Mode select bit A This bit has different functions, depending on the state of ELSxB and ELSxA. When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. To select the level of your initial output, write the appropriate value to MSxA while ELSxB:A = 00. Then configure all bits in the TSCx as required for your application. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 85 Freescale Semiconductor, Inc. Capture/Compare Unit When ELSxB:A ≠ 00, this read/write bit selects input capture mode or unbuffered OC/PWM mode. This bit should be set for unbuffered PWM operation. MS0A and MS1A are active only when MS0B = 0. MS2A and MS3A are active only when MS2B = 0. Reset clears the MSxA bit. 1 = Unbuffered OC/PWM operation 0 = Input capture operation NOTE: Freescale Semiconductor, Inc... Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/level select bits When channel x is a PWM channel, ELSxB and ELSxA control the channel x output behavior when a pulse width match occurs. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 5 shows the configuration selected by ELSxB and ELSxA in unbuffered PWM mode. Reset clears the ELSxB and ELSxA bits. Table 5. Unbuffered PWM Mode and Level Selection MSxB: MSxA X0 X1 01 01 01 01 ELSxB: ELSxA 00 00 00 01 10 11 Mode Output preset Output preset Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Configuration Set initial output level high Set initial output level low TCHx pin under port control; set initial output level low. Toggle output on PWM match Clear output on PWM match Set output on PWM match TIM08 Reference Manual — Rev. 1.0 86 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions TOVx — Toggle on overflow When channel x is a buffered or unbuffered OC/PWM channel, this read/write bit controls the behavior of the channel x output when the timer counter overflows. Reset clears the TOVx bit 1 = Channel x pin toggles on timer counter overflow 0 = Channel x pin does not toggle on timer counter overflow NOTE: When TOVx is set, a timer counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — PWM 100% duty cycle This read/write bit forces the duty cycle of buffered and unbuffered OC/PWM signals to 100%. As Figure 33 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. CHxMAX affects only the logic level of the channel x pin; pulse width matches can continue to occur and set the channel x flag. Reset clears the CHxMAX bit. Freescale Semiconductor, Inc... PERIOD TIMER OVERFLOW TCHx PULSE WIDTH MATCH CHxMAX Figure 33. CHxMAX Latency TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 87 Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Registers These read/write registers are used as the 16-bit compare register for PWM functions. These registers contain the pulse width match value for the PWM function. The state of the channel registers after reset is unknown. In unbuffered PWM mode (MSxB:MSxA = 0:1), pulse width matches are inhibited between writes to TCHxH and TCHxL. This prevents another match from occurring until the new pulse width value is written. The STHX instruction can be used to write to TCHxH:L. Freescale Semiconductor, Inc... If a timer channel register is not used for a PWM function, it can be used as a storage location. TIM08 Reference Manual — Rev. 1.0 88 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Unbuffered Pulse Width Modulation (PWM) Functions TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 34. Timer Channel Registers (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 89 Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions TIM pins TCH0 and TCH2 may be used as a buffered PWM function. This is accomplished by linking two unbuffered PWM channels together to form one buffered PWM channel. When used as buffered PWM pins, TCH0 and TCH2 each have two dedicated 16-bit compare registers (TCHxH/L), two 16-bit comparators, and interrupt generation logic. The 16-bit modulo counter value, TCNT, is used as the timing reference for all buffered PWM functions. When the programmed contents of a timer channel register match TCNT, the 16-bit comparator generates a PWM match, and certain automatic actions are initiated. These automatic actions can be a hardware interrupt request and state changes at the related timer output pin. When generating a buffered PWM signal, the value in the timer channel registers determines the pulse width of the PWM signal, and the value of the timer modulo registers determines the period of the PWM signal. Refer to Figure 30. The toggle on overflow feature links the overflow of the 16-bit modulo counter to the buffered PWM channel. See Pulse-Width Modulation (PWM) Concepts and Buffered PWM Signal Generation for more information on the basic operation of this function. Freescale Semiconductor, Inc... PERIOD TIMER OVERFLOW PULSE WIDTH TCHx PULSE WIDTH MATCH Figure 35. PWM Period and Pulse Width TIM08 Reference Manual — Rev. 1.0 90 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions When the PWM match occurs, a status flag CHxF is set in TSCx. Figure 36, in the previous section, shows the timing of CHxF relative to the bus clocks, as well as the timing relationships for state changes and interrupts described in the following paragraphs. A PWM pin can be programmed to change states when a PWM match occurs, thereby determining the pulse width of the PWM signal. TSCx control bits ELSxA and ELSxB determine the output state of the pin on a PWM match. An unbuffered PWM channel can be programmed to toggle, clear, or set the TCHx pin on a PWM match. Table 6 for the control bit configurations to select the state of a PWM signal pin. If the interrupt enable bit (CHxIE) for this PWM function is set in TSCx, a CPU interrupt is generated on a PWM match. If the interrupt is disabled, CHxF can be polled by software to determine when a match has occurred. See CPU Interrupts for details on interrupt operation. Freescale Semiconductor, Inc... NOTE: DMA service requests are not available in buffered PWM mode. To generate a signal with 100% duty cycle, use the CHxMAX bit in the TSCx. To generate a signal with 0% duty cycle, program the PWM channel to either set or clear (not toggle) on PWM match, then clear the TOVx bit to start a 0% duty cycle signal. NOTE: In PWM signal generation, do not program the PWM channel to toggle on PWM match. Toggling on PWM match prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on PWM match can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. To use TCH0 as a buffered PWM pin, set the MS0B bit in TSC0. This will disable TCH1 as a TIM pin, and it will revert to port control. TSC0 controls and monitors the buffered PWM function, and TSC1 is unused. The channel 0 registers, TCH0H:TCH0L, initially control the pulse width on the TCH0 pin. Writing to the channel 1 registers enables the channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the channel registers (0 or 1) last written to control the pulse width. Figure 36. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 91 Freescale Semiconductor, Inc. Capture/Compare Unit To use TCH2 as a buffered PWM pin, set the MS2B bit in TSC2. This will disable TCH3 as a TIM pin, and it will revert to port control. TSC2 controls and monitors the buffered PWM function, and TSC3 is unused. The channel 2 registers, TCH2H:TCH2L, initially control the pulse width on the TCH2 pin. Writing to the channel 3 registers enables the channel 3 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the channel registers (2 or 3) last written to control the pulse width. NOTE: Freescale Semiconductor, Inc... In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. The software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. TIM08 Reference Manual — Rev. 1.0 92 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK R‡ R† W‡ W† W* W† Freescale Semiconductor, Inc... TCNT TCH0H:TCH0L CH0F TCH1H:TCH1L TMODH:TMODL TOF 0056 0050 0050 0051 0052 0050 0053 0054 0055 0050 0056 0000 0001 0002 0050 { WRITE CH0F = 0 0040 0056 0056 0001 0056 READ CH0F = 1 0040 TCH0 PIN TSC0 TSC 24 00 TOGGLE ON OVERFLOW CLEAR ON PWM MATCH a4 24 80 R† READ DATA W† WRITE DATA R‡ READ TSC0 W‡ WRITE TSC0 W* WRITE TCH1L a4 NAME IT12, IT23 TCNTH:TCNTL TCH0H:TCHOL CH0F TMODH:TMODL TOF TCH0 pin TSC0 TSC DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 data register for output compare value CH0F bit in TSC0 register Timer counter modulo register Timer counter overflow flag (TOF) bit in TSC register Timer channel 0 output pin Timer status and control register, channel 0 Timer status and control register Figure 36. Buffered PWM Timing TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 93 Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform PWM functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following in buffered PWM mode: • • • Flags pulse width matches Enables PWM interrupts Selects initial level of TCHx output pin Selects buffered PWM operation Selects high, low, or toggling output on PWM match Selects output toggling on timer overflow Selects 100% PWM duty cycle Bit 7 CH0F CH0IE Write Reset: 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... • • • • TSC0 Read: TSC2 Read: Write: Reset: Bit 7 CH2F 6 CH2IE 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 Bit 0 CH2MAX 0 0 0 0 Figure 37. Timer Channel Status and Control Registers (TSC0, TSC2) CHxF — Channel x flag When channel x is a buffered PWM channel, CHxF is set when the value in the timer counter registers matches the value in the timer channel x registers. When CPU interrupts are enabled (CHxE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the TIM08 Reference Manual — Rev. 1.0 94 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions clearing sequence is complete, writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. DMA service requests may not be used with buffered PWM functions. Writing a one to this bit has no effect. Reset clears the CHxF bit. 1 = PWM match on channel x 0 = No PWM match on channel x CHxIE — Channel x interrupt enable Freescale Semiconductor, Inc... This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register should be cleared to select channel x CPU interrupts. DMA service requests cannot be used with buffered PWM mode. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode select bit B This bit should be set for buffered PWM operation. MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register, and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register, and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 95 Freescale Semiconductor, Inc. Capture/Compare Unit MSxA — Mode select bit A This bit has different functions, depending on the state of ELSxB and ELSxA. When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. To select the level of your initial output, write the appropriate value to MSxA while ELSxB:A = 00. Then configure all bits in the TSCx as required for your application. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... When ELSxB:A ≠ 00, this bit is unused for buffered PWM operation. NOTE: Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/level select bits When channel x is a buffered PWM channel, ELSxB and ELSxA control the channel x output behavior when a pulse width match occurs. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 6 shows the configuration selected by ELSxB and ELSxA in buffered PWM mode. Reset clears the ELSxB and ELSxA bits. Table 6. Buffered PWM Mode and Level Selection MSxB: MSxA X0 X1 1X 1X 1X 1X ELSxB: ELSxA 00 00 00 01 10 11 Mode Output preset Output preset Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Configuration Set initial output level high Set initial output level low TCHx pin under port control; set initial output level. Toggle output on PWM match Clear output on PWM match Set output on PWM match TIM08 Reference Manual — Rev. 1.0 96 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions TOVx — Toggle on overflow When channel x is a buffered or unbuffered OC/PWM channel, this read/write bit controls the behavior of the channel x output when the timer counter overflows. Reset clears the TOVx bit. 1 = Channel x pin toggles on timer counter overflow 0 = Channel x pin does not toggle on timer counter overflow NOTE: When TOVx is set, a timer counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — PWM 100% duty cycle This read/write bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 38 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. CHxMAX affects only the logic level of the channel x pin; pulse width matches can continue to occur and set the channel x flag. Reset clears the CHxMAX bit. Freescale Semiconductor, Inc... PERIOD TIMER OVERFLOW TCHx PULSE WIDTH MATCH CHxMAX Figure 38. CHxMAX Latency TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 97 Freescale Semiconductor, Inc. Capture/Compare Unit Timer Channel Registers These read/write registers are used as the 16-bit compare register for PWM functions. These registers contain the pulse width match value for the PWM function. The state of the channel registers after reset is unknown. In buffered PWM mode (MSxB = 1), pulse width matches are inhibited between writes to TCHxH and TCHxL of the active channel. This prevents another match from occurring until the new pulse width value is written. Output compares are allowed between writes to TCHxH and TCHxL of the inactive channel. The STHX instruction can be used to write to TCHxH:L. If a timer channel register is not used for a PWM function, it can be used as a storage location. Freescale Semiconductor, Inc... 98 TIM08 Reference Manual — Rev. 1.0 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Capture/Compare Unit Buffered Pulse Width Modulation (PWM) Functions TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 39. Timer Channel Registers (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com 99 Freescale Semiconductor, Inc. Capture/Compare Unit Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 100 Capture/Compare Unit For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Freescale Semiconductor, Inc... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Timer DMA Select Register (TDMA) . . . . . . . . . . . . . . . . . . . . . . . .102 CPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Timer Overflow Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Output Compare/PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . .109 DMA Service Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Output Compare/PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . .113 Introduction The TIM is capable of generating one interrupt for the timer counter overflow, and one for each of the channels. These interrupts can be masked by clearing the Interrupt Enable bit for each interrupt source. See Timer Status and Control Register for more information on setting up the timer counter overflow interrupt. See Timer Channel Status and Control Registers, Timer Channel Status and Control Registers, Timer Channel Status and Control Registers, Timer Channel Status and Control Registers, and Timer Channel Status and Control Registers for more information on setting up interrupts for each of the TIM channels. NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 101 Freescale Semiconductor, Inc. Interrupts Interrupts Each interrupt can be directed to the central processor unit (CPU08), and the channel interrupts can generate service requests directed to the direct memory access (DMA) module for processing, if available. See Timer DMA Select Register (TDMA) for more information on selecting the interrupt destination for each timer channel. NOTE: Freescale Semiconductor, Inc... DMA service requests cannot be enabled for buffered OC/PWM operation. This could cause incorrect flag clearing. Timer DMA Select Register (TDMA) The timer DMA register selects either the CPU or the DMA module to service TIM interrupts. These bits are cleared on reset, selecting the CPU to process interrupts. NOTE: This register is available only on microcontrollers with a DMA module. If no DMA module is included, do not enable the bits described in Figure 40. If those bits are enabled, no CPU interrupts for that channel will be generated or serviced. The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36.. TDMA Read: Write: Reset: 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 0 DMA3S DMA2S DMA1S DMA0S 3 2 1 0 NOTE: Figure 40. Timer DMA Select Register (TDMA) TIM08 Reference Manual — Rev. 1.0 102 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts Timer DMA Select Register (TDMA) DMA3S — DMA channel 3 select This read/write bit enables the DMA to process TIM interrupts on timer channel 3. Reset clears the DMA3S bit. 1 = Timer channel 3 generates DMA service requests 0 = Timer channel 3 generates CPU interrupt requests DMA2S — DMA channel 2 select This read/write bit enables the DMA to process TIM interrupts on timer channel 2. Reset clears the DMA2S bit. 1 = Timer channel 2 generates DMA service requests 0 = Timer channel 2 generates CPU interrupt requests DMA1S — DMA channel 1 select This read/write bit enables the DMA to process TIM interrupts on timer channel 1. Reset clears the DMA1S bit. 1 = Timer channel 1 generates DMA service requests 0 = Timer channel 1 generates CPU interrupt requests DMA0S — DMA channel 0 select This read/write bit enables the DMA to process TIM interrupts on timer channel 0. Reset clears the DMA0S bit. 1 = Timer channel 0 generates DMA service requests 0 = Timer channel 0 generates CPU interrupt requests Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 103 Freescale Semiconductor, Inc. Interrupts CPU Interrupts The TIM provides interrupt sources to the CPU08 through the system integration module (SIM). The SIM receives all interrupt requests for the CPU and decodes interrupt priorities when multiple requests are received. The SIM is different on each microcontroller, and the interrupt priorities can change. A common TIM interrupt priority scheme, as implemented on the MC68HC708XL36, is described in this section. See the applicable technical data book for the correct interrupt priority. Freescale Semiconductor, Inc... NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. If more than one TIM interrupt is received by the SIM, the CH0 interrupt is processed first, followed by CH1, CH2, and CH3 interrupts, with the timer overflow interrupt processed last. The TIM channels will provide interrupts to the CPU if the associated DMA select bit is cleared, as discussed in Timer DMA Select Register (TDMA). Table 7. TIM Interrupt Priority Source CH0F CH1F CH2F CH3F TOF Local Mask CH0IE CH1IE CH2IE CH3IE TOE I Global Mask Vector Address $FFF4–$FFF5 $FFF2–$FFF3 $FFF0–$FFF1 $FFEE–$FFEF $FFEC–$FFED The interrupt flags (TOF, CH0F, CH1F, CH2F, and CH3F) are set and cleared regardless of the value of the interrupt enable bits (TOE, CH0IE, CH1IE, CH2IE and CH3IE). The interrupt flags are set when a timer overflow, input capture, output compare, or PWM match occurs. Each interrupt flag is cleared by reading the interrupt flag while it is set, and then writing a logic 0 to the flag. If another flag has been received TIM08 Reference Manual — Rev. 1.0 104 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts CPU Interrupts between the read and write of the flag, the flag will not be cleared, indicating that another interrupt has occurred. If the interrupt enable bit is set for a particular flag, a CPU interrupt will be generated. Timer Overflow Timing Freescale Semiconductor, Inc... Figure 41 shows the timing relationships between the MCU bus clocks, the 16-bit timer counter, and the timer overflow flag and interrupt. In this example, the modulo counter is programmed to overflow at $0054. The counter clock is running at the fastest clock rate, which is the same frequency as IT12. The counter value changes on the falling edge of IT12. When the counter reaches the TMOD value, TOF is set at the next falling edge of IT12. When TOF is set, the TCHx pin is toggled if TOVx is set in the corresponding TSCx register. TOF also generates the timer overflow interrupt signal to the CPU08. As long as TOF = 1, the interrupt is pending. The interrupt is cleared by clearing TOF: read TOF = 1, then write TOF = 0. Figure 41 shows another example of a timer overflow occurring. In this example, the counter clock is slower than the bus clock. Notice that on the counter overflow, the TOF is set on the falling edge of IT12 following the TMOD match. This immediately resets the timer counter to 0. Input Capture Timing Figure 43 shows the timing relationship between the bus clocks, the counter, and the input capture circuit for a CPU interrupts on timer channel 1. A change on the TCH1 input pin occurring before the falling edge of IT12 is recognized by the input capture circuit. On the next falling edge of IT12, CH1F is set and the channel 1 CPU interrupt signal, timintcx, is asserted. On the falling edge of IT23, the value of the counter is latched into TCH1. As long as CH1F = 1, the interrupt is pending. The interrupt is cleared by clearing CH1F: read CH1F = 1, then write CH1F = 0. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 105 Freescale Semiconductor, Inc. Interrupts IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK R§ R† W† * W§ Freescale Semiconductor, Inc... TCNTH:TCNTL 0052 0053 0054 0000 0001 TMODH:TMODL 0054 0054 0054 TOF { READ TOF = 1 WRITE 0 TO FLAG TOGGLE ON OVERFLOW TCHx TIM OVERFLOW INTERRUPT READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R§ READ TSC R‡ READ TSC0 R† READ DATA W† WRITE DATA W‡ WRITE TSC0 W§ WRITE TSC * NAME IT12, IT23 TCNTH:TCNTL TMODH:TMODL TOF TCHx DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register 16-bit value in TMOD register TOF bit in TSC register Timer channel pin with TOVx enabled in TSCx Figure 41. CPU Counter Overflow Interrupt Timing Example A TIM08 Reference Manual — Rev. 1.0 106 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts CPU Interrupts IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK TCNTH:TCNTL 0053 0054 0000 0001 R§ R† W† * W§ Freescale Semiconductor, Inc... TMODH:TMODL 0054 0054 TOF { READ TOF = 1 WRITE 0 TO FLAG TOGGLE ON OVERFLOW W§ WRITE TSC TCHx TIM OVERFLOW INTERRUPT * READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R§ READ TSC R† READ DATA W† WRITE DATA NAME IT12, IT23 TCNTH:TCNTL TMODH:TMODL TOF TCHx DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register 16-bit value in TMOD register TOF bit in TSC register Timer channel pin with TOVx enabled in TSCx Figure 42. CPU Counter Overflow Interrupt Timing Example B TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 107 Freescale Semiconductor, Inc. Interrupts IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS COUNTER CLOCK TCNTH:TCNTL TCH1 0019 0020 0021 0022 0023 0024 0025 0026 cc 4c ← EDGE OCCURRING BEFORE ↓ IT12 IS RECOGNIZED. Freescale Semiconductor, Inc... CH1F timintc1 timintd1 INTERNAL READ/WRITE TCH0H:TCH0L TSC1 4c 0021 cc 4c R† W† R† READ ch1f = 1 W† WRITE ch1f = 0 NAME IT12, IT23 TCNTH:TCNTL TCH1 CH1F timintc1 timintd1 TCH0H:TCH0L TSC1 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 1 input pin CH1F bit in TSC1 register TIM channel 1 CPU interrupt signal TIM channel 1 DMA service request signal 16-bit value in TCH0 register Timer status and control register, channel 1 Figure 43. CPU Input Capture Interrupt Timing Example TIM08 Reference Manual — Rev. 1.0 108 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts CPU Interrupts Output Compare/PWM Timing Freescale Semiconductor, Inc... Figure 44 shows the timing relationships between the MCU bus clocks, the 16-bit timer counter, and the timer output compare/PWM match flag and interrupt. In this example, the OC/PWM match is programmed to occur at $0050, and the modulo counter is programmed to overflow at $0054. The counter clock is running at the fastest clock rate, which is the same frequency as IT12. The counter value changes on the falling edge of IT12. When the counter reaches the TCH0 value ($0050), CH0F is set at the next falling edge of IT12. When CH0F is set, the TCH0 pin is cleared, as specified in the TSC0 register. CH0F also generates the TIM channel 0 CPU interrupt signal, timintc0, to the CPU08. While CH0F = 1, the interrupt is pending. The interrupt is cleared by clearing CH0F: read CH0F = 1, then write CH0F = 0. When the counter reaches the TMOD value, TOF is set, TCH0 toggles, and the timer overflow interrupt signal is asserted, as described in Timer Overflow Timing. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 109 Freescale Semiconductor, Inc. Interrupts IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK R‡ R† W‡ W† R§ * R† W§ W† Freescale Semiconductor, Inc... TCNT TCH0 CH0F TIMINTCSS0 TMODH:TMODL TCH0 TOF 0050 0050 0051 0052 0050 0053 0054 0000 0050 0001 { WRITE CH0F = 0 READ CH0F = 1 0054 0054 TOGGLE ON OVERFLOW CLEAR ON OC/PWM 0054 READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R§ READ TSC R‡ READ TSC0 R† READ DATA W† WRITE DATA W‡ WRITE TSC0 W§ WRITE TSC * NAME IT12, IT23 TCNTH:TCNTL TCHo CH0F timintc0 TMODH:TMODL TCH0 TOF DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer status and control register, channel 0 CH0F bit in TSC0 register TIM channel 0 CPU interrupt signal 16-bit value in TCH0 register Timer channel 0 output pin Timer counter overflow flag in TSC Figure 44. CPU Output Compare/PWM Interrupt Example TIM08 Reference Manual — Rev. 1.0 110 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts DMA Service Requests DMA Service Requests NOTE: DMA service requests are available only on microcontrollers with a DMA module. If no DMA module is included, do not enable the bits described in Figure 40. If those bits are enabled, no CPU interrupts for that channel will be generated or serviced. The TIM provides service requests to the DMA. The DMA service request priorities are determined by the DMA channel assignment. The TIM channels will provide service requests to the DMA if the associated DMA select bit is set, as discussed in Timer DMA Select Register (TDMA). Freescale Semiconductor, Inc... NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. The interrupt flags (CH0F, CH1F, CH2F, and CH3F) are set and cleared regardless of the value of the interrupt enable bits (CH0IE, CH1IE, CH2IE, and CH3IE). The interrupt flags are set when an input capture or output compare occurs. Each interrupt flag is cleared by reading or writing to the low byte of the associated channel data register (TCHxL). Reading or writing the interrupt flag will have no affect on the condition of the flag. If the interrupt enable bit is set for a particular flag, a DMA service request will be generated. Input Capture Timing Figure 45 shows the timing relationship between the bus clocks, the counter, and the input capture circuit for a DMA service request on timer channel 3. A change on the TCH3 input pin occurring before the falling edge of IT12 is recognized by the input capture circuit. On the next falling edge of IT12, CH3F is set and the channel 3 DMA service request signal, timintdx, is asserted. On the falling edge of IT23, the value of the counter is latched into TCH3. As long as CH3F = 1, the service request is pending. The service request is cleared when the DMA reads the low byte of the channel register, TCH3L. A write to TCH3L will also clear the TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 111 Freescale Semiconductor, Inc. Interrupts CH3F. Reads and writes of TSC3 do not clear the flag or pending service request. IT12 IT23 INTERNAL ADDRESS BUS Freescale Semiconductor, Inc... INTERNAL DATA BUS COUNTER CLOCK TCNTH:TCNTL TCH3 00C0 00C1 00C2 $c8 $48 $c2 00C3 00C4 00C5 00C6 00C7 00C8 ← EDGE OCCURRING BEFORE ↓ IT12 IS RECOGNIZED. CH3F TIMINTD3 DMA SERVICE REQUEST PENDING INTERNAL READ/WRITE TCH3H:TCH3L TSC3 48 R‡ READ CH3F = 1 R‡ W‡ R§ 00c2 c8 W‡ WRITE CH3F = 0 R§ READ TCH3L 48 NAME IT12, IT23 TCNTH:TCNTL TCH3 CH3F timintd3 TCH3H:TCH3L TSC3 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 3 input pin CH3F bit in TSC3 register TIM channel 3 DMA service request signal 16-bit value in TCH3 register Timer status and control register, channel 3 Figure 45. DMA Input Capture Service Request Timing Example TIM08 Reference Manual — Rev. 1.0 112 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Interrupts DMA Service Requests Output Compare/PWM Timing Freescale Semiconductor, Inc... Figure 46 shows the timing relationships between the MCU bus clocks, the 16-bit timer counter, and the timer output compare/PWM match flag and service request. In this example, the OC/PWM match is programmed to occur at $0050, and the modulo counter is programmed to overflow at $0054. The counter clock is running at the fastest clock rate, which is the same frequency as IT12. The counter value changes on the falling edge of IT12. When the counter reaches the TCH0 value ($0050), CH0F is set at the next falling edge of IT12. When CH0F is set, the TCH0 pin is cleared, as specified in the TSC0 register. CH0F also generates the TIM channel 0 DMA service request signal, timintd0, to the DMA module. While CH0F = 1, the service request is pending. The service request is cleared when the DMA writes to TCH0L. A read of TCH0L will also clear CH0F. Reads and writes of TSC3 do not clear the flag or pending service request. When the counter reaches the TMOD value, TOF is set, TCH0 toggles, and the timer overflow interrupt signal is asserted, as described in Timer Overflow Timing. NOTE: The DMA module will not service buffered OC/PWM interrupts. These bits should be cleared for both channels used in a buffered OC/PWM mode. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Interrupts For More Information On This Product, Go to: www.freescale.com 113 Freescale Semiconductor, Inc. Interrupts IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS INTERNAL READ/WRITE COUNTER CLOCK R‡ R† W† W‡ W§ $19 * Freescale Semiconductor, Inc... TCNTH:TCNTL TCH0H:TCH0L TMODH:TMODL 0050 0050 0051 0052 0050 0053 0000 0001 0050 0002 0003 0019 0053 CLEARED BY WRITE TO TCH0L 0053 0053 CH0F timintd0 TCH0 TOF READ/WRITE IS NOT USUALLY IN BACK-TO-BACK CYCLES. R‡ READ TSC0 R† READ TSC0 DATA W§ WRITE TCH0L W† WRITE TSC0 DATA W‡ WRITE TSC0 * NAME IT12, IT23 TCNTH:TCNTL TCH0 CH0F timintd0 TCH0H:TCH0L TSC0 DESCRIPTION Bus clocks used by CPU08, DMA, TIM and all modules on MCU 16-bit value in TCNT register Timer channel 0 output pin CH0F bit in TSC0 register TIM channel 0 DMA service request signal 16-bit value in TCH0 register Timer status and control register, channel 0 Figure 46. DMA Output Compare/PWM Service Request Example TIM08 Reference Manual — Rev. 1.0 114 Interrupts For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Special Modes Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Freescale Semiconductor, Inc... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction In addition to the user mode, the M68HC08 Family of microcontrollers supports several other operating modes. The function of the TIM is described for wait, stop, and monitor modes. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Special Modes For More Information On This Product, Go to: www.freescale.com 115 Freescale Semiconductor, Inc. Special Modes Wait Mode Wait mode is entered by executing the WAIT instruction in the CPU08. Wait mode is a low-power mode in which the CPU clocks are stopped, and the bus clocks to the TIM continue to run. The TIM functions are active and all TIM counters and prescalers continue counting during wait mode. A timer interrupt may cause the CPU08 to exit wait mode if interrupts are not masked. Freescale Semiconductor, Inc... All TIM registers retain their states in wait mode. If a DMA is available, it can service a TIM interrupt without causing the CPU to have to exit wait mode. This can be used to fill a buffer with input capture data or to transmit a buffer full of OC/PWM data. A DMA interrupt can be used to exit the CPU from wait and then to use or refill the buffer data as needed. This feature allows the MCU to conserve power, avoid long interrupt service latency, and potentially reduce code size due to fewer necessary interrupt service routines. Stop Mode Stop mode is entered by executing the STOP instruction in the CPU08. Stop mode is the lowest power-consumption mode, with the bus clocks stopped to both the CPU08 and the TIM. The MCU remains in STOP mode until the STOP bit is negated by the CPU or by a reset. All TIM counters and prescalers stop counting while the STOP bit is asserted. All TIM registers retain their states in stop mode. TIM08 Reference Manual — Rev. 1.0 116 Special Modes For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Special Modes Monitor Mode Monitor Mode Monitor mode gives access to an on-chip monitor providing basic debugging facilities through a single wire serial interface to a host computer. The debug monitor provides basic commands to read and write the memory contents of the 68HC08 through an interface with a host computer. The monitor commands can be used to provide all the features normally found in a monitor, such as loading in user code, adding breakpoints, and modifying CPU, peripheral, and I/O register contents. If the MCU application is designed correctly, the monitor can be used to debug code in the embedded ROM part. Freescale Semiconductor, Inc... NOTE: The monitor mode is different on each microcontroller, and the sequence used to enter this mode may change. monitor mode, as implemented on the MC68HC708XL36, is described in this section. On the MC68HC708XL36, monitor mode is entered by placing 2 x VDD on pin IRQ1/VPP, grounding PTC1, and pulling PTC0 high. The execution of an SWI (software interrupt) instruction or the execution of a hardware reset while holding PTA0 high will start the monitor and send a break to the host computer. The communication interface with the host computer is a standard asynchronous communication interface with the transmitted and received data sent over the same wire. For more information on monitor mode, see the appropriate technical data book. The TIM is active in monitor mode. Software loaded into RAM by the debug monitor can access TIM registers and interrupts can be enabled and generated. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Special Modes For More Information On This Product, Go to: www.freescale.com 117 Freescale Semiconductor, Inc. Special Modes Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 118 Special Modes For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Freescale Semiconductor, Inc... General TIM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 PWMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 PWM Controlled RC Digital to Analog Converter . . . . . . . . . . . . . . .131 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Servo Loop Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Using the HC708XL36 DMA with the TIM . . . . . . . . . . . . . . . . . . . .144 Functional Description of Program . . . . . . . . . . . . . . . . . . . . . . .146 System Resource Configuration . . . . . . . . . . . . . . . . . . . . . . . . .146 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 119 Freescale Semiconductor, Inc. Applications Introduction The TIM allows flexible configurations to service a variety of timing applications. Users familiar with the HC05 16-bit timer modules will discover that the TIM provides all the same features (input capture, output compare, interrupt on overflow) with additional functionality. Extra features include configurable channels, buffered/unbuffered PWM capability in conjunction with a modulo register, toggle on overflow, more control of the timer counter (stop and reset commands), and DMA servicing of the TIM on some devices. The following applications are discussed in this section: • • • • General TIM Information PWM Controlled RC Digital to Analog Converter Servo Loop Motor Control Using the HC708XL36 DMA with the TIM Freescale Semiconductor, Inc... NOTE: All software examples in this section were written for the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 120 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications General TIM Information General TIM Information The following sections detail the basic functions of the TIM including input capture, output compare, unbuffered PWM, and buffered PWM by presenting the following applications: • • • Input capture Output compare PWMs Freescale Semiconductor, Inc... Input Capture The input capture function is useful for measuring pulse widths or periods of signals and for establishing functional time references (delays, state machines, etc.) to external events. The TIM allows processor interrupts or polling on rising and/or falling edges, time reference adjustment (via the modulo register), and time base adjustment (via the prescaler). The following example illustrates a general-purpose input capture routine that will measure the period of an incoming signal. Table 8 details possible resolutions and frequency ranges for each timer prescaler. Range indicates the range of input frequencies that can be measured, as determined by the value in the modulo register. Resolution indicates the frequency at which the timer counter is incremented by one bit. NOTE: Higher input frequencies may be difficult to measure without using a DMA or external circuitry. Table 8. Range and Resolution for Period Input/Output* Prescaler 1 2 4 8 16 32 64 Range (Hz) 122 - 8.0 M 61 - 4.0 M 30.5 - 2.0 M 15.3 - 1.0 M 7.6 - 500 k 3.8 - 250 k 1.9 - 125 k Resolution 125 ns 250 ns 500 ns 1 µs 2 µs 4 µs 8 µs * Assumes 8 MHz bus clock, 65K counts max TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 121 Freescale Semiconductor, Inc. Applications * * Application example for TIM Reference Manual * * This software will feature the 68HC08XL36 Timer * Interface Module in an input capture example. * A specified channel will receive pulses or periods * and interrupt the CPU on a specified edge. * * Register Equates TSC equ $20 ;Timer Status & Control Register $20 TDMA equ $21 ;Timer DMA Select Register $21 TCNTH equ $22 ;Timer Counter Register Hi $22 TCNTL equ $23 ;Timer Counter Register Lo $23 TMODH equ $24 ;Timer Counter Modulo Register Hi $24 TMODL equ $25 ;Timer Counter Modulo Register Lo $25 TSC0 equ $26 ;Timer Channel 0 Status & Control Register $26 TCH0H equ $27 ;Timer Channel 0 Register Hi $27 TCH0L equ $28 ;Timer Channel 0 Register Lo $28 TSC1 equ $29 ;Timer Channel 1 Status & Control Register $29 TCH1H equ $2a ;Timer Channel 1 Register Hi $2a TCH1L equ $2b ;Timer Channel 1 Register Lo $2b TSC2 equ $2c ;Timer Channel 2 Status & Control Register $2c TCH2H equ $2d ;Timer Channel 2 Register Hi $2d TCH2L equ $2e ;Timer Channel 2 Register Lo $2e TSC3 equ $2f ;Timer Channel 3 Status & Control Register $2f TCH3H equ $30 ;Timer Channel 3 Register Hi $30 TCH3L equ $31 ;Timer Channel 3 Register Lo $31 PORTE equ $08 ;Port E, TIM port * Miscellaneous Equates BIT0 equ $00 BIT1 equ $01 BIT2 equ $02 BIT3 equ $03 BIT4 equ $04 BIT5 equ $05 BIT6 equ $06 BIT7 equ $07 CHOFFSET equ $00 ;ch0 = 0 offset, ch1 = 3 offset, chx = 3x offset * TIM status and control register bits PRESCLR equ $00 ;prescaler xxxxx000 (bus clock / 1) TOE equ $00 ;timer overflow interrupt enable x0xxxxxx * Channel CHXIE MODE EDGE x status and control register bits equ $40 ;channel interrupt enable x0xxxxxx equ $00 ;mode select bits xx00xxxx (input capture) equ $04 ;edge select bits xxxx00xx (rising edge) Freescale Semiconductor, Inc... * Variables in RAM org $0050 ;start of RAM * Application assembly code org $6e00 ;start of ROM TIM08 Reference Manual — Rev. 1.0 122 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications General TIM Information ICAP_INIT: * set up channel x for input capture mov #TOE+$30+PRESCLR,TSC ;stop and reset TIM, select prescaler, TOE ldx #TSC0+CHOFFSET ;point to channel x SCR lda #CHXIE+MODE+EDGE sta ,x ;store channel ICAP control info cli bclr BIT5,TSC bra * ;enable CPU interrupts (delete this line if polling) ;enable timer counter ;wait for interrupt (to poll monitor channel x flag) * channel x interrupt service routine for ICAPx CHISR equ * pshh ;save h register lda TSC0+CHOFFSET ;read channel x flag bclr BIT7, TSC0+CHOFFSET ;clear it read time value from channel register pulh ;retrieve h register rti ;return from interrupt routine Freescale Semiconductor, Inc... * * Application vectors org fdb fdb fdb fdb org fdb $ffee CHISR CHISR CHISR CHISR $fffe ICAP_INIT Output Compare Output compares are useful for generating one-shot or periodic output signals, or for internal software events (delays, periodic execution). The TIM allows control over the duration and polarity of an output signal, an option for buffered or unbuffered implementation, time reference adjustment (via the timer modulo register), and time base adjustment (via the prescaler). Note that buffered output compares can provide precise signal changes on the outputs, but each use two TIM channels. The following section of code uses an output compare port to generate a periodic output signal. See Table 8 for a list of ranges and resolutions over all prescaler values. Range indicates the range of frequencies that can be output, as determined by the value in the modulo register. Resolution indicates the frequency at which the timer counter is incremented by one bit. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 123 Freescale Semiconductor, Inc. Applications * * Application example for TIM Reference Manual * * This software will feature the 68HC08XL36 Timer * Interface Module in an output compare example. * A signal with 50% duty cycle and specified period * will be generated on a specified channel. * * Register Equates TSC equ $20 ;Timer Status & Control Register $20 TDMA equ $21 ;Timer DMA Select Register $21 TCNTH equ $22 ;Timer Counter Register Hi $22 TCNTL equ $23 ;Timer Counter Register Lo $23 TMODH equ $24 ;Timer Counter Modulo Register Hi $24 TMODL equ $25 ;Timer Counter Modulo Register Lo $25 TSC0 equ $26 ;Timer Channel 0 Status & Control Register TCH0H equ $27 ;Timer Channel 0 Register Hi $27 TCH0L equ $28 ;Timer Channel 0 Register Lo $28 TSC1 equ $29 ;Timer Channel 1 Status & Control Register TCH1H equ $2a ;Timer Channel 1 Register Hi $2a TCH1L equ $2b ;Timer Channel 1 Register Lo $2b TSC2 equ $2c ;Timer Channel 2 Status & Control Register TCH2H equ $2d ;Timer Channel 2 Register Hi $2d TCH2L equ $2e ;Timer Channel 2 Register Lo $2e TSC3 equ $2f ;Timer Channel 3 Status & Control Register TCH3H equ $30 ;Timer Channel 3 Register Hi $30 TCH3L equ $31 ;Timer Channel 3 Register Lo $31 PORTE equ $08 ;Port E, TIM port Freescale Semiconductor, Inc... $26 $29 $2c $2f * Miscellaneous Equates BIT0 equ $00 BIT1 equ $01 BIT2 equ $02 BIT3 equ $03 BIT4 equ $04 BIT5 equ $05 BIT6 equ $06 BIT7 equ $07 CHOFFSET equ $00 ;ch0 = 0 offset, ch1 = 3 offset, chx = 3x offset PERHI equ $80 ;16.4ms period, 4.1ms offset from bus clock PERLO equ $00 * TIM status and control register bits PRESCLR equ $00 ;prescaler xxxxx000 (bus clock / 1) TOE equ $00 ;timer overflow interrupt enable x0xxxxxx * Channel CHIE MOD EDG TOV x status and control register bits equ $00 ;channel interrupt enable x0xxxxxx equ $10 ;mode select bits xx00xxxx (output compare) equ $04 ;edge select bits xxxx00xx (toggle output) equ $00 ;toggle on overflow bit xxxxxx0x * Variables in RAM org $0050 ;start of RAM * Application assembly code org $6e00 ;start of ROM TIM08 Reference Manual — Rev. 1.0 124 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications General TIM Information OC_INIT: * set up channel x for output compare mov #TOE+$30+PRESCLR,TSC ;stop and reset TIM, select prescaler, TOE ldx #TSC0+CHOFFSET lda #CHIE+MOD+EDG+TOV sta ,x lda sta lda sta #PERHI 1,x #PERLO 2,x ;point to channel x SCR ;store channel ICAP control info ;set up signal period ;store in timer channel reg. (hi byte) ;store low byte ;enable timer counter (generate signal) bclr BIT5,TSC Freescale Semiconductor, Inc... bra * * interrupt service routines * Application vectors org $fffe fdb OC_INIT PWMs PWMs are useful for generating signals to motor or gauge drivers, switching power supplies, and low-cost D/A converters. The TIM contains a special modulo register that controls the period of the PWM and a channel register that controls the pulse width (duty cycle). Other features include a buffered or unbuffered option, polarity control, toggle on overflow, and a 100% duty cycle option. The eight basic steps for setting up a PWM channel on the TIM are as follows: 1. Stop and reset the timer counter module using bits 4-5 of the timer status and control register. 2. Select a value for the timer counter modulo register and a timer prescaler with bits 0-2 of the timer status and control register to provide the required PWM period. 3. Load the appropriate timer channel register with the initial required pulse width. 4. Configure the timer channel for buffered/unbuffered output compare operation using bits 4 and 5 of the appropriate timer channel status and control register. 5. Select the timer counter “toggle on overflow” option using bit 1 of the appropriate timer channel status and control register. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 125 Freescale Semiconductor, Inc. Applications 6. Configure the timer channel to force the output to the “inactive” level on a successful compare (toggle on output compare should not be used) using bits 2 and 3 of the appropriate timer channel status and control register. 7. Enable output compare interrupts (if used) using bit 0 of the appropriate timer channel status and control register. 8. Enable the timer counter using bit 5 of the timer status and control register. Freescale Semiconductor, Inc... The following code details a general-purpose unbuffered PWM routine (all parameters are user-selectable). * * This software will feature the 68HC08XL36 Timer * Interface Module in an unbuffered PWM example. * A periodic waveform with specified duty cycle * and period will be generated on a specified * channel. * * Register Equates TSC equ $20 ;Timer Status & Control Register $20 TDMA equ $21 ;Timer DMA Select Register $21 TCNTH equ $22 ;Timer Counter Register Hi $22 TCNTL equ $23 ;Timer Counter Register Lo $23 TMODH equ $24 ;Timer Counter Modulo Register Hi $24 TMODL equ $25 ;Timer Counter Modulo Register Lo $25 TSC0 equ $26 ;Timer Channel 0 Status & Control Register TCH0H equ $27 ;Timer Channel 0 Register Hi $27 TCH0L equ $28 ;Timer Channel 0 Register Lo $28 TSC1 equ $29 ;Timer Channel 1 Status & Control Register TCH1H equ $2a ;Timer Channel 1 Register Hi $2a TCH1L equ $2b ;Timer Channel 1 Register Lo $2b TSC2 equ $2c ;Timer Channel 2 Status & Control Register TCH2H equ $2d ;Timer Channel 2 Register Hi $2d TCH2L equ $2e ;Timer Channel 2 Register Lo $2e TSC3 equ $2f ;Timer Channel 3 Status & Control Register TCH3H equ $30 ;Timer Channel 3 Register Hi $30 TCH3L equ $31 ;Timer Channel 3 Register Lo $31 PORTE equ $08 ;Port E, TIM port $26 $29 $2c $2f * Miscellaneous Equates BIT0 equ $00 BIT1 equ $01 BIT2 equ $02 BIT3 equ $03 BIT4 equ $04 BIT5 equ $05 BIT6 equ $06 BIT7 equ $07 CHOFFSET equ $00 ;ch0 = 0 offset, ch1 = 3 offset, chx = 3x offset DUTYHI equ $80 ;50% duty cycle DUTYLO equ $00 PERHI equ $FF ;8.2ms period PERLO equ $FF TIM08 Reference Manual — Rev. 1.0 126 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications General TIM Information * TIM status and control register bits PRESCLR equ $00 ;prescaler xxxxx000 (bus clock / 1) TOE equ $00 ;timer overflow interrupt enable x0xxxxxx * Channel x status and control register bits CHIE equ $40 ;channel interrupt enable x0xxxxxx MOD equ $10 ;mode select bits xx00xxxx (output compare) EDG equ $0c ;edge select bits xxxx00xx (set output) TOV equ $02 ;toggle on overflow bit xxxxxx0x * Variables in RAM org $0050 ;start of RAM * Application assembly code org $6e00 ;start of ROM UNBUF_INIT: * set mov ldx lda sta lda sta lda sta up channel x for unbuffered PWM #TOE+$30+PRESCLR, TSC ;stop and reset TIM, select prescaler, TOE #TSC0+CHOFFSET ;point to channel x SCR (H reg = 00) #CHIE+MOD+EDG+TOV ;enable i, OC, set output, toggle ,x ;store channel ICAP control info #DUTYHI ;specified duty cycle 1,x ;store in timer channel reg. #DUTYLO 2,x ;store specified period Freescale Semiconductor, Inc... mov #PERHI,TMODH mov #PERLO,TMODL cli bclr BIT5,TSC bra * ;enable CPU interrupts (delete this line if polling) ;enable timer counter ;wait for interrupt (to poll monitor channel x flag) * channel x interrupt service routine for OCx CHISR equ * pshh ;save h register lda TSC0+CHOFFSET ;read channel x flag bclr BIT7,TSC0+CHOFFSET ;clear it * change duty cycle here (write to channel register) pulh ;retrieve h register rti ;return from interrupt routine * Application vectors org fdb fdb fdb fdb $ffee CHISR CHISR CHISR CHISR org $fffe fdb UNBUF_INIT TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 127 Freescale Semiconductor, Inc. Applications The limitations of unbuffered PWMs are most apparent during the pulse width/duty cycle update process (for example, changing the timer channel register). The least reliable method is to randomly update the channel register, which can take up to two full periods to synchronize the output. A more reliable method is to update the channel register during a timer overflow interrupt routine, which can still cause one period of synchronization if the pulse width is decreased to 16 bus cycles or less (worst case interrupt latency before channel register update). The most reliable method is to update the channel register during an output compare interrupt routine. However, even this method will unsynchronize the output for one period when changing from a very high duty cycle to a very low duty cycle (for example, the interrupt routine latency exceeds the toggle and pulse width). Since there are no infallible unbuffered PWM methodologies, the TIM has been designed to configure buffered PMW channels, at the trade-off of using two TIM channels. Buffered PWM channels are initialized using the same eight steps listed above and are implemented by alternately writing one of two timer channel registers. The software must track which channel register was last written. The following code details a general purpose buffered PWM routine using the TIM (all parameters are user selectable). Freescale Semiconductor, Inc... 128 TIM08 Reference Manual — Rev. 1.0 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications General TIM Information Freescale Semiconductor, Inc... * * This software will feature the 68HC08XL36 Timer * Interface Module in an buffered PWM example. * A periodic waveform with specified duty cycle * and period will be generated on a specified * channel. * * Register Equates TSC equ $20 ;Timer Status & Control Register $20 TDMA equ $21 ;Timer DMA Select Register $21 TCNTH equ $22 ;Timer Counter Register Hi $22 TCNTL equ $23 ;Timer Counter Register Lo $23 TMODH equ $24 ;Timer Counter Modulo Register Hi $24 TMODL equ $25 ;Timer Counter Modulo Register Lo $25 TSC0 equ $26 ;Timer Channel 0 Status & Control Register TCH0H equ $27 ;Timer Channel 0 Register Hi $27 TCH0L equ $28 ;Timer Channel 0 Register Lo $28 TSC1 equ $29 ;Timer Channel 1 Status & Control Register TCH1H equ $2a ;Timer Channel 1 Register Hi $2a TCH1L equ $2b ;Timer Channel 1 Register Lo $2b TSC2 equ $2c ;Timer Channel 2 Status & Control Register TCH2H equ $2d ;Timer Channel 2 Register Hi $2d TCH2L equ $2e ;Timer Channel 2 Register Lo $2e TSC3 equ $2f ;Timer Channel 3 Status & Control Register TCH3H equ $30 ;Timer Channel 3 Register Hi $30 TCH3L equ $31 ;Timer Channel 3 Register Lo $31 PORTE equ $08 ;Port E, TIM port $26 $29 $2c $2f * Miscellaneous Equates BIT0 equ $00 BIT1 equ $01 BIT2 equ $02 BIT3 equ $03 BIT4 equ $04 BIT5 equ $05 BIT6 equ $06 BIT7 equ $07 CHOFFSET equ $00 ;ch0 = 0 offset, ch2 = 6 offset DUTYHI equ $80 ;50% duty cycle DUTYLO equ $00 PERHI equ $FF ;8.2ms period PERLO equ $FF * TIM status and control register bits PRESCLR equ $00 ;prescaler xxxxx000 (bus clock / 1) TOE equ $00 ;timer overflow interrupt enable x0xxxxxx * Channel x status and control register bits CHIE equ $40 ;channel interrupt enable x0xxxxxx MOD equ $30 ;mode select bits xx00xxxx (buffered PWM) EDG equ $0c ;edge select bits xxxx00xx (set output) TOV equ $02 ;toggle on overflow bit xxxxxx0x * Variables in RAM org $0050 ;start of RAM track rmb 1 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 129 Freescale Semiconductor, Inc. Applications * Application assembly code org $6e00 ;start of ROM BUFF_INIT: * set up channel x for unbuffered PWM bset BIT0,track ;set tracker flag mov #TOE+$30+PRESCLR,TSC ldx #TSC0+CHOFFSET lda #CHIE+MOD+EDG+TOV sta ,x lda sta lda sta #DUTYHI 1,x #DUTYLO 2,x ;stop and reset TIM, select prescaler, TOE ;point to channel x SCR (H reg = 00) ;enable i, buff, set output, toggle ;store channel OC control info ;specified duty cycle ;store in timer channel reg. Freescale Semiconductor, Inc... mov #PERHI,TMODH mov #PERLO,TMODL cli bclr BIT5,TSC bra * ;store specified period in MOD reg. ;enable CPU interrupts (delete this line if polling) ;enable timer counter (start PWM) ;wait for interrupt (to poll monitor channel x flag) * channel x interrupt service routine for OCx CHISR equ * pshh ;save h register lda TSC0+CHOFFSET ;read channel x flag bclr BIT7,TSC0+CHOFFSET ;clear it brset BIT0,track,JUMP ;determine which reg. to update bset BIT0,track ;set tracker flag * change duty cycle (write to channel 1 or 3 register) bra EXIT JUMP bclr BIT0,track ;clear tracker flag * change duty cycle (write to channel 2 or 4 register) EXIT pulh ;retrieve h register rti ;return from interrupt routine * Application vectors org fdb fdb fdb fdb org fdb $ffee CHISR CHISR CHISR CHISR $fffe BUFF_INIT TIM08 Reference Manual — Rev. 1.0 130 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications PWM Controlled RC Digital to Analog Converter PWM Controlled RC Digital to Analog Converter Pulse width modulation (PWM) is the process of using signal processing techniques to control the pulse width of a digital signal. The PWM signal is manipulated by software instructions and can be used in a variety of applications. One application is the design of a digital-to-analog converter (DAC). The PWM signal is sent out of the MCU and directly drives an RC circuit as shown in Figure 47. This circuit will produce a filtered average of the PWM signal on the output. Freescale Semiconductor, Inc... IN R C OUT Figure 47. RC Circuit For example, a 25% duty cycle PWM signal is shown in Figure 48. The “high” part of the signal is called the pulse width and in this example represents 25% of the PWM period. The “low” part of the signal represents 75% of the PWM signal. The entire cycle of the entire PWM signal is called the “PWM period.” The PWM frequency is 1/(PWM period). PULSE WIDTH PWM PULSE PWM PERIOD Figure 48. 25% Duty Cycle PWM Signal When a PWM signal is fed into the RC circuit shown in Figure 47, a pseudo DC signal is created at the output of the RC circuit. This signal will have some low amplitude ripple dependent on the RC time constant of the circuit and the frequency of the PWM signal. The average DC signal is related to the length of the pulse width of the PWM signal. The equation is as follows: TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 131 Freescale Semiconductor, Inc. Applications Average DC signal = Duty Cycle * (PWM high voltage — PWM low voltage) For example, if there is a 5-volt, 50% duty cycle PWM signal driving the RC circuit in Figure 47, the average DC out voltage would be 2.5 volts. If the PWM duty cycle was changed to 85%, the average DC output voltage would be 4.25 volts. By varying the duty cycle, the user can design a simple digital-to-analog converter. Freescale Semiconductor, Inc... Analysis There are four parameters that affect the DC output voltage: the capacitor, resistor, PWM frequency, and the PWM pulse width. As the preceding example has shown, the PWM pulse width (duty cycle) directly affects the filtered DC output level. The frequency and the RC time constant affect the ripple of the output. As the resistor and/or the capacitor are increased, there will be less ripple on the output due to the increased time constant of the circuit. Also, as the frequency increases, the ripple's frequency will increase, but its amplitude will decrease because the time for the voltage to rise or fall will be shortened. When a rising voltage pulse is fed into the RC circuit, the output voltage responds according to the following equation: VOUT = VIN – VIN e –t RC where VOUT is the output voltage, VIN is the input voltage, t is time after pulse, and RC is the time constant. When a falling voltage pulse is fed into the RC circuit, the output voltage responds according to the following equation: VOUT = VIN e –t RC Figure 49 illustrates the transient voltage waveform of an RC network driven by a PWM signal. In this example, a 10-kHz, 50% duty cycle, 5-volt digital signal drives a resistor of 1 k and a capacitor of 1F. TIM08 Reference Manual — Rev. 1.0 132 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications PWM Controlled RC Digital to Analog Converter 0.5 0.4 VOLTAGE 0.3 0.2 0.1 0.0 0.00 0.50 1.00 1.50 2.00 Freescale Semiconductor, Inc... PWM CYCLES Figure 49. 10-kHz, 50% Duty Cycle RC Transient Response Since the TIM uses a PWM signal, the equation to define the output voltage is not as obvious as the equations stated above. There are two different equations defining the output of the signal. A single equation cannot define the characteristics of the signal. In this case, the high part of the PWM signal has an equation and the low part of the PWM signal has an equation. The following equations define the voltage after the high part of the PWM signal (VOUTHIGH the voltage at the low part of the PWM signal VOUTLOW, and the average voltage of the high and low parts during the PWM period VOUTAVG). VOUTHIGH(n) = VIN – VIN e VIN–VOUTLOW (n–1) VIN ))] –[tc+(–RC ln( RC VOUTLOW(n) = VOUTHIGH(n) e –t(1–d) RC VOUTAVG(n) = VOUTHIGH(n)–VOUTHIGH(n) + VOUTLOW(n) 2 where d = duty cycle in decimal form t = length of time of the signal's period n = the number of PWM periods TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 133 Freescale Semiconductor, Inc. Applications Finding the output voltage at a particular time now becomes an iterative process. Write a small program with the preceding equations for your analysis. For example, use the circuit described earlier: a 5-volt 50% duty cycle, 10-kHz PWM signal driving a 1-k resistor and a 1-F capacitor network. Find the output voltage after the duty cycle of the second PWM period and the average voltage after one PWM period. After calculating with t = .0001 and d = 0.5, the following results are shown in Table 9. Table 9. Output Voltages Time Period VOUTHIGH 0 0.24385288 0.46450009 VOUTLOW 0 0.23196003 0.44184615 VOUTAVG 0 0.23790645 0.45317312 Freescale Semiconductor, Inc... 0 1 2 Therefore, the output voltage after the duty cycle of the second PWM period is 0.46450009 volts. The average voltage after one PWM period is 0.23790645 volts. A graph of the output voltage over 60 time periods is shown in Figure 50. Figure 50. 10-kHz, 50% Duty Cycle RC Response TIM08 Reference Manual — Rev. 1.0 134 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications PWM Controlled RC Digital to Analog Converter Hardware Figure 47 shows that the DAC circuit is designed with an RC network. If the DAC were designed to drive a load, the extra load would change the time constant of the RC network. This in turn would change the transient and steady state responses. In order to buffer the RC network, feed the output into an op amp configured as a voltage follower. Since the inputs to the op amp are very high impedance, they should not affect the response of the RC network. The output of the op amp can now drive larger loads. This circuit is shown in Figure 51. Freescale Semiconductor, Inc... — +VCC OUT –VEE IN R C + Figure 51. Buffered Output Software The following code initializes the timer for PWM and then enables the timer to start outputting the PWM signal. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 135 Freescale Semiconductor, Inc. Applications **************************************************************************** **************************************************************************** * * * Implementation of an unbuffered PWM with the Timer * * * **************************************************************************** * * * File Name: UB_PWM.RTN Copyright (c) Motorola 1994 * * * * Curent Revision: 1.00 * * Current Release Level: ESS * * Current Revision Release Date: 03/23/94 * * * * Current Release Written By: Mark Glenewinkel * * Motorola CMCU Applications - Austin, Texas * * * * Assembled Under: IASM08 (P&E Microcomputer Systems, Inc.) Ver.: 1.00 * * * * Documentation File Name: UB_PWM.DOC Revision: 1.00 * * * * Brief Description of Routine Purpose: * * This routine uses the Timer to implement a PWM signal. * * * * Part Family Software Routine Works With: HC08 * * * * Worst Case Execution (Cycles): 28 * * Routine Size (Bytes): 20 * * Stack Space Used (Bytes): 0 * * RAM Used (Bytes): 0 * * * * Global Variables Used: None * * Subroutines Used: None * * * * Full Functional Description of Routine Design: * * In order to setup a PWM waveform, the following must be configured: * * 1) Stop the timer, reset the timer counter (set TSTOP & TRST bits in TSC)* * 2) Write to the 16 bit modulo counter to set the PWM period (TMODH:L) * * 3) Write to the 16 bit Output Compare register for the appropriate * * timer channel. This sets the PWM pulse width (TCHxH:L) * * 4) Write to the timer channel status and control register (TSCx) * * Disable the output compare interrupt (CHxIE = 0) * * Configure for unbuffered PWM (MSxB:A = 01) * * Configure to clear output line on PWM match (ELSxB:A = 10) * * Configure overflow to toggle timer channel (TDVx = 1) * * Disable max 100% duty cycle (CHxMAX = 0) * * 5) Enable the timer to start counting (clear TSTOP in TSC) * * * **************************************************************************** * * * Update History: * * Rev: Author: Date: Description of Change: * * ----------------------------------* * ESS 1.0 Glenewinkel 03/23/94 Original Release * * * **************************************************************************** **************************************************************************** * * * Motorola reserves the right to make changes without further notice to any * * product herein to improve reliability, function, or design. Motorola does * * not assume any liability arising out of the application or use of any * * product, circuit, or software described herein; neither does it convey any* Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 136 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications PWM Controlled RC Digital to Analog Converter Freescale Semiconductor, Inc... * license under its patent rights nor the rights of others. Motorola * * products are not designed, intended, or authorized for use as components * * in systems intended for surgical implant into the body, or other * * applications intended to support life, or for any other application in * * which the failure of the Motorola product could create a situation where * * personal injury or death may occur. Should Buyer purchase or use Motorola * * products for any such intended or unauthorized application, Buyer shall * * indemnify and hold Motorola and its officers, employees, subsidiaries, * * affiliatees, and distributors harmless against all claims, costs, damages, * * and expenses, and reasonable attorney fees arising out of, directly or * * indirectly, any claim of personal injury or death associated with such * * unintended or unauthorized use, even if such claim alleges that Motorola * * was negligent regarding the design or manufacture of the part. Motorola * * and the Motorola Logo are registered trademarks of Motorola Inc. * * * **************************************************************************** **************************************************************************** * * * Part Specific Framework Includes Section * * * $INCLUDE 'H708XL36.FRK' ;Device specific equates file * **************************************************************************** * * * Equates for Main Routine * * * **************************************************************************** * * * None * * **************************************************************************** * * * RAM Definitions for Main Routine * * * **************************************************************************** * * org RAM_Start * None * * **************************************************************************** * * * Program Initialization * * * * Code needed to initialize processor resources is placed here. * * * **************************************************************************** org Start mov EPROM_Start #$30,TSC ; start of HC708XL36 EPROM ($6E00) * * * ; stop the timer counter ; reset timer counter ; select prescaler (timclk = busclock) Write the value for the required PWM frequency With a 4 MHz bus, $01FF in the modulo register creates a 7.8125kHz signal or a 128usec period mov mov #$01,TMODH #$FF,TMODL ; modulo byte high ; modulo byte low TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 137 Freescale Semiconductor, Inc. Applications * * * * Write the value for the required PWM pulse width For a 25% pulse width, the pulse width will be equal to 32usec Write $0080 to timer channel 0 output compare mov mov * * * * * * #$00,TCH0H #$80,TCH0L ; timer channel 0 high ; timer channel 0 low Write to timer channel 0 status and control reg CH0E=0, disable output compare interrupt MS0B:MS0A=01, unbuffered PWM, output compare ELS0B:ELS0A=10, clear output line on compare TOV0=1, enable timer counter toggle on overflow CH0MAX=0, disable max 100% duty cycle mov #%00011010,TSC0 ; timer CH0 status & ctrl Freescale Semiconductor, Inc... * Enable the timer - start counter by clearing STOP bit bclr 5,TSC ; timer status & ctrl **************************************************************************** * * * Main Program Loop * * * **************************************************************************** LOOP nop bra ; infinite loop while PWM ; is running LOOP **************************************************************************** * * * Interrupt Service Routines for Main Routine * * * **************************************************************************** org fdb RESET Start **************************************************************************** TIM08 Reference Manual — Rev. 1.0 138 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Servo Loop Motor Control Servo Loop Motor Control This application section details the implementation of a basic proportional derivative (PD) closed-loop speed control for a brush motor using four ICs (including an MC68HC08XL36), two opto discretes, and less than 200 bytes of code. The TIM provides a flexible timing source for control systems which require extra features such as varying drive capability or non-volatile storage of parametric data. A typical MCU control system is mathematically modeled in the discrete time domain since data is sampled (not continuous). A straightforward control system using the MC68HC08XL36 and an MPM3004 TMOS H-bridge is characterized by the PD loop shown in Figure 52. The transfer function Gc(s) consists of the PD control, and Gp(s) represents a power amplifier, motor, and load, where s is a complex variable with both real and imaginary parts. In Gc(s), the proportional term, called Kp, is resolved (to a power of two) using simple shifts, and the derivative term, called KDs, of f(t) is approximately dƒ(t) dt t = kT Freescale Semiconductor, Inc... ≅ 1 [ƒ (kT) – ƒ (k – 1)T] Τ where f(kT) is the current sample of the controlled input and f(k-1)T is the previous sample. Finally, the term kDs is realized as the rate of change of the difference between the measured and desired period of motor shaft rotation. KP R (s) + – KDs GC (s) + ƒ (t) + µ (ƒ) GP (s) Figure 52. PD Loop Flow TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 139 Freescale Semiconductor, Inc. Applications The circuit in Figure 53 represents a block diagram of servo loop motor control. The TIM is configured to input capture a feedback signal from an infrared detector on channel 1 and will output an 8-bit buffered PWM using channels 2 and 3. The H-bridge driver block is represented by an MPM3004, capable of controlling bidirectional currents of 10 A (continuous) at 60 V. It is driven indirectly by the microcontroller via the level shifter block, consisting of two MC34151 dual inverting gate drivers. Finally, the opto-sensor block is represented by an MRD750 Schmitt trigger detector, which is coupled to an MLED71 infrared emitter that monitors motor rotation through a slotted disc on the motor shaft. Freescale Semiconductor, Inc... 4 MC68HC08 MCU LEVEL SHIFTER 4 H-BRIDGE DRIVER MOTOR OPTO SENSOR Figure 53. Servo Loop Motor Control Block Diagram The complexity of the software algorithm executed by the microcontroller is dictated by the environment or desired performance of the motor. The justification for adding a derivative term can be understood by realizing that an underdamped proportional-only controller causes overshoot and ringing because of the system's attempt to reduce the error term to zero too rapidly. The derivative term works to compensate the rate of change of the error term. On the other hand, the derivative term also reduces the response time of the loop. Additionally, an integral term can be added (not included in this example) for low pass filtering or where the steady state error is potentially large. The following code has been simplified for clarity to 8-bit math and will only drive the motor in one direction, so more stringent system specifications may require some additions to the code. Also, TIM08 Reference Manual — Rev. 1.0 140 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Servo Loop Motor Control initialization, direction control, and diagnostic (for example, motor stall) routines have been omitted to keep this application generic. Finally, this application example is a conversion of Motorola Application Note Basic Servo Loop Motor Control Using the MC68HC05B6 MCU, order number AN1120/D. Please refer to it for more details. * Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 141 Freescale Semiconductor, Inc. Applications * Application example for TIM Reference Manual * * This software features the 68HC08XL36 Timer Interface Module in an * electronic motor speed control application. An input capture channel (IC1) * will be used as a tachometer pulse input and two output compare channels (OC2 * & OC3) will be used in conjunction with a control line to a motor driver * circuit (switching amplifier with 8-bit PWM input). * * Register Equates TSC equ $20 ;Timer Status & Control Register $20 TDMA equ $21 ;Timer DMA Select Register $21 TCNTH equ $22 ;Timer Counter Register Hi $22 TCNTL equ $23 ;Timer Counter Register Lo $23 TMODH equ $24 ;Timer Counter Modulo Register Hi $24 TMODL equ $25 ;Timer Counter Modulo Register Lo $25 TSC0 equ $26 ;Timer Channel 0 Status & Control Register $26 TCH0H equ $27 ;Timer Channel 0 Register Hi $27 TCH0L equ $28 ;Timer Channel 0 Register Lo $28 TSC1 equ $29 ;Timer Channel 1 Status & Control Register $29 TCH1H equ $2a ;Timer Channel 1 Register Hi $2a TCH1L equ $2b ;Timer Channel 1 Register Lo $2b TSC2 equ $2c ;Timer Channel 2 Status & Control Register $2c TCH2H equ $2d ;Timer Channel 2 Register Hi $2d TCH2L equ $2e ;Timer Channel 2 Register Lo $2e TSC3 equ $2f ;Timer Channel 3 Status & Control Register $2f TCH3H equ $30 ;Timer Channel 3 Register Hi $30 TCH3L equ $31 ;Timer Channel 3 Register Lo $31 PORTE equ $08 ;Port E, where PWM happens! Freescale Semiconductor, Inc... * Miscellaneous Equates BIT0 equ $00 BIT1 equ $01 BIT2 equ $02 BIT3 equ $03 BIT4 equ $04 BIT5 equ $05 BIT6 equ $06 BIT7 equ $07 * Variables org edge1h rmb edge1l rmb edge2h rmb edge2l rmb period rmb pwidth rmb desper rmb deltnew rmb deltold rmb deltadc rmb toggle rmb in RAM $0050 1 1 1 1 1 1 1 1 1 1 1 ;start of RAM ;high byte of first edge count ;low byte of first edge count ;high byte of second edge count ;low byte of second edge count ;timer value of feedback signal ;pulsewidth for motor - must be initialized ;desired feedback period - must be initialized ;current error value ;error value from last sample ;rate of change compensated error ;toggle for PWM buffers * Application assembly code org $6e00 ;start of ROM TIM08 Reference Manual — Rev. 1.0 142 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Servo Loop Motor Control TIMER_INIT: * set up channels 2 & 3 for PWM mov #$30,TSC ;stop and reset the TIM, set prescaler to 1 mov #$FF,TMODL clr TMODH mov #$3A,TSC2 mov #pwidth,TCH2L clr TCH2H bset BIT0,toggle ;set 31.4 kHz frequency for PWM output ; ;buff. PWM, no int., fall. edge, TOV2 ;load initial pulsewidth into ;channel register ;write channel 3 reg. on next update Freescale Semiconductor, Inc... *set up channel 1 for input capture mov #$48,TSC1 ;ICAP, fall. edge, enable int. cli bclr BIT5,TSC ;clear interrupt bit; enable CPU interrupts ;enable timer counter bra * * * Interrupt service routine(s) * * channel 1 interrupt service routine is entered * when a falling edge is encountered on ICAP1 CH1ISR equ * pshh lda TSC1 bclr BIT7,TSC1 gfly1 brclr BIT7,TSC1,gfly1 ldhx TCH1H sthx edge1h lda #$FF delay dbnza delay lda TSC1 bclr BIT7,TSC1 gfly2 brclr BIT7,TSC1,gfly2 ldhx TCH1H sthx edge2h lda edge2l sub edge1l sta period mov deltnew,deltold lda desper sub period blo incspd lsla sta deltnew lda deltold sub deltnew sta deltadc lda deltnew sub deltadc sta deltadc lda pwidth sub deltnew bhi check pwmdn lda #$10 savepwm brset BIT0,toggle,set3 ;save h register ;read channel 1 flag ;clear it ;wait for next falling edge ;read timer counter value ;store first edge value ;debounce time ;read channel 1 flag ;clear it ;wait for next falling edge ;read timer counter value ;store second edge value ;calculate period ;store period ;read previous error & store it ;load desired period ;subtract actual period ;if difference is < 0, inc. speed ;multiply error by 2 ;store new error value ;read old error value ;get rate of change of error ;store rate of change of error ;read new error value ;apply de/dt correction ;store it ;read current motor pulse ;apply correction ;if positive, check magnitude ;decide which channel reg. to write TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 143 Freescale Semiconductor, Inc. Applications bset BIT0,toggle sta TCH2L clr TCH2H bra exit bclr BIT0,toggle sta TCH3L clr TCH3H bra exit cmp #$10 blo pwmdn bra savepwm lsla sta deltnew lda deltold sub deltnew sta deltadc lda pwidth sub deltadc blo savepwm pulh rti ;write channel 3 next time ;store pulse length in channel 2 reg. set3 ;write channel 2 next time ;store pulse length in channel 3 reg. check incspd Freescale Semiconductor, Inc... exit ;check for minimum ;set minimum ;save decremented pulse length ;multiply error by 2 ;store new error value ;read previous error value ;get rate of change of error ;store rate of change compensation ;read current pulse width ;apply correction ;check for saturation or correction = 0 ;retrieve h register * Application vectors org fdb org fdb $fff2 CH1ISR $fffe TIMER_INIT Using the HC708XL36 DMA with the TIM The MC68HC708XL36 timer module can be configured to let the DMA handle updating output compare registers when a timer interrupt occurs. When the contents of the timer counter registers matches the value stored in the timer output compare registers, a service request can be generated to signal the DMA to store a new value in the timer output compare registers, thus scheduling the next output compare. In the example that follows, the device is configured to have the DMA sequentially fetch a 16-bit value from a 32-byte table in RAM and store those values in the timer output compare registers as each output compare interrupt occurs. Using the DMA for this type of processing frees up the CPU for other tasks, since DMA processing can be set up to have minimal impact on CPU activity. TIM08 Reference Manual — Rev. 1.0 144 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Using the HC708XL36 DMA with the TIM For example, the timer and DMA will be configured to continually repeat the waveform shown below. Freescale Semiconductor, Inc... 12 3 4 56 7 89 10 11 12 13 14 15 16 Figure 54. Waveform On Output Compare Pin (PTE5) The output compare values that are used to generate the above waveform are stored in RAM beginning at location $60 as shown in the table below: Table 10. Output Compare Values Graph Point 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Address in RAM $60 $62 $64 $66 $68 $6A $6C $6E $70 $72 $74 $76 $78 $7A $7C $7E $0000 $03E8 $0A28 $11F8 $1518 $1900 $2260 $2710 $2AF8 $3520 $3A98 $3F48 $43F8 $48A8 $4D58 $5528 Data (1st o/c) (1st o/c + 125us) (2nd o/c + 200us) (3rd o/c + 250us) (4th o/c + 100us) (5th o/c + 125us) (6th o/c + 300us) (7th o/c + 150us) (8th o/c + 125us) (9th o/c + 325us) (10th o/c + 175us) (11th o/c + 150us) (12th o/c + 150us) (13th o/c + 150us) (14th o/c + 150us) (15th o/c + 200us) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 145 Freescale Semiconductor, Inc. Applications Functional Description of Program The program uses DMA channel 0 for transfers and timer channel 1 for output compares. The bus rate is 8 MHz (125 ns per cycle). The modulo timer counter registers are set to generate a counter rollover at $6FFF. The timer output compare registers (TCH1H:TCH1L) are initialized to $5555. The first output compare interrupt will occur when the value in the output compare registers matches the value in the timer counter registers. At that time the DMA will transfer the value of $0000 to the output compare registers to generate the first scheduled service request when the timer changes from $6FFF to $0000. The second scheduled interrupt will occur 125 µs later (1000 cycles * 125 ns per cycle = $03E8). The third output compare interrupt will occur 200 µs later (second output compare + third pulse = 125 µs + 200 µs = $0A28). Each output compare interrupt will generate a DMA service request. This process will therefore continue until all 16-bit table entries have been transferred. The waveform will be continually repeated from this point on each time the timer changes from $6FFF to $0000. Freescale Semiconductor, Inc... System Resource Configuration DMA • Write DMA Source Base Address (D0SH:D0SL = $0060) – Beginning address for the table of output compare values in RAM. • Write DMA Destination Base Address (D0DH:D0DL = $002A) – Address of Timer Channel 1 Output Compare Registers (TCH1H:TCH1L). • Configure DMA Channel 0 Control Register (D0C = $89) – Source/destination address set to increment/static. – Select word transfers. – DMA transfer source set to Timer Channel 1 service request. • Configure DMA Status and Control Register (DSC = $10) – Enable loop mode for DMA Channel 0. TIM08 Reference Manual — Rev. 1.0 146 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Using the HC708XL36 DMA with the TIM • Configure DMA Block Length Register (D0BL = $20) – Number of bytes in RAM table = 32 = $20. • Configure DMA Control Register 1 (DC1 = 2) – Enable DMA Channel 0. Timer • Configure Timer Status and Control Register (TSC = $30): – Stop and reset Timer. Freescale Semiconductor, Inc... • Initialize Timer 1 Output Compare Registers (TCH1H:TCH1L): – First output compare at $5555. • Configure Modulo Timer (TMODH:TMODL): – Counter rollover at $6FFF cycles. • Configure Timer DMA Select (TDMA = 2): – DMA service for Timer Channel 1 service requests. • Configure Timer Channel 1 Status and Control Register (TSC1 = $54): – Enable output compare interrupts. – Set up for output compare with toggle (see note below). – Disable toggle on Timer overflow. • Configure Timer Status and Control Register (TSC = 0): – Start timer. – Prescaler set to system clock/1 (default condition). NOTE: When the output compare function is enabled, the associated output compare pin is set to a logic 1. The first toggle will be a negative transition and will occur when the timer counter reaches $5555. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 147 Freescale Semiconductor, Inc. Applications Main Routine: Branch to self forever (bra *) end of main routine .pagewidth !132 **************************************************************************** **************************************************************************** * * Using the HC708XL36 DMA with the Timer * **************************************************************************** * * File Name: DMATEX.RTN Copyright (c) Motorola 1994 * * Current Revision: 1.00 * Current Release Level: PA * Current Revision Release Date: 03/13/94 * * Current Release Written By: Mark Johnson * Motorola CMCU Applications - Austin, Texas * * Assembled Under: IASM08 (P&E Microcomputer Systems, Inc.) Ver.: 1.01 * * Documentation File Name: DMATEX.TXT Revision:1.00 * * Brief Description of Routine Purpose: This routine uses the DMA to service * Timer interrupts and schedule output * compares. * * Part Family Software Routine Works With: HC08 * * Worst Case Execution (Cycles): Infinite Loop * Routine Size (Bytes): 47 * Stack Space Used (Bytes): 0 * RAM Used (Bytes): 32 * * Global Variables Used: None * Subroutines Used: None * * Full Functional Description Of Routine Design: * * The program uses DMA Channel 0 for transfers and Timer Channel 1 for * output compares. The bus rate is 8MHz (125 ns per cycle). The modulo * timer counter registers are set to generate a counter rollover at $6FFF. * The timer output compare registers (TCH1H:TCH1L) are initialized to * $5555. The first output compare interrupt will occur when the * value in the output compare registers matches the value in * the timer counter registers. At that time the DMA will transfer the value * of $0000 to the output compare registers to generate the first scheduled * interrupt when the timer changes from $6FFF to $0000. The second * scheduled interrupt will occur 125us later (1000 cycles * 125ns per * cycle = $03E8). The third output compare interrupt will occur 200 us * later (125us + 200us = 1000 + 1600 = 2600 = $0A28). This process will * continue until all 16-bit table entries have been transferred. The * waveform will be continually repeated from this point on when the * timer changes from $6FFF to $0000. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 148 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Using the HC708XL36 DMA with the TIM * System Resource Configuration: * * DMA * 1) Write DMA Source Base Address (D0SH:D0SL = $0060): * - beginning address for the table of output * compare values in RAM. * 2) Write DMA Destination Base Address (D0DH:D0DL = $002A): * - address of Timer Channel 1 Output Compare Registers * (TCH1H:TCH1L). * 3) Configure DMA Channel 0 Control Register (D0C = $89): * - source/destination address set to increment/static. * - select word transfers. * - DMA transfer source set to Timer Channel 1 * service request. * 4) Configure DMA Status and Control Register (DSC = $10): * - enable loop mode for DMA Channel 0. * 5) Configure DMA Block Length Register (D0DL = $20): * - number of bytes in RAM table = 32 = $20. * 6) Configure DMA Control Register 1 (DC1 = 2): * - enable DMA Channel 0. * * Timer * * 1) Configure Timer Status and Control Register (TSC = $30): * - stop and reset Timer. * 2) Initialize Timer 1 Output Compare Registers (TCH1H:TCH1L): * - first output compare at $5555. * 3) Configure Modulo Timer (TMODH:TMODL): * - counter rollover at $6FFF cycles. * 4) Configure Timer DMA select (TDMA = 2): * - DMA service for Timer Channel 1 interrupts. * 5) Configure Timer Channel 1 Status and Control Reg. (TSC1 = $54): * - enable output compare interrupts. * - set up for output compare with toggle * (* see note below). * - disable toggle on Timer overflow. * 6) Configure Timer Status and Control Register (TSC = 0): * - start Timer. * - prescaler set to system/1 (default condition). * * Note: When the output compare function is enabled, the associated output * compare pin is set to a logic 1. The first toggle will be a negative * transition and will occur when the Timer counter reaches $5555. * * Main Routine: * * Branch to self forever (bra *) * * end of main routine * * **************************************************************************** * * Update History: * Rev: Author: Date: Description of Change: * ----------------------------------* PA 1.0 Johnson 3/13/94 Original Release * **************************************************************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 149 Freescale Semiconductor, Inc. Applications **************************************************************************** * * Motorola reserves the right to make changes without further notice to any * product herein to improve reliability, function, or design. Motorola does * not assume any liability arising out of the application or use of any * product, circuit, or software described herein; neither does it convey any * license under its patent rights nor the rights of others. Motorola * products are not designed, intended, or authorized for use as components * in systems intended for surgical implant into the body, or other * applications intended to support life, or for any other application in * which the failure of the Motorola product could create a situation where * personal injury or death may occur. Should Buyer purchase or use Motorola * products for any such intended or unauthorized application, Buyer shall * indemnify and hold Motorola and its officers, employees, subsidiaries, * affiliates, and distributors harmless against all claims, costs, damages, * and expenses, and reasonable attorney fees arising out of, directly or * indirectly, any claim of personal injury or death associated with such * unintended or unauthorized use, even if such claim alleges that Motorola * was negligent regarding the design or manufacture of the part. Motorola * and the Motorola Logo are registered trademarks of Motorola Inc. * **************************************************************************** **************************************************************************** $PAGE * **************************************************************************** * * Part Specific Framework Includes Section * * Place the assembler statement ($INCLUDE) to include the part specific * framework for the target part. * **************************************************************************** * $NOLIST $INCLUDE 'H708XL36.FRK' ;Device specific equates file * $LIST * **************************************************************************** * * Equates for Main Routine * **************************************************************************** * Table_start equ $60 * **************************************************************************** * * RAM Definitions for Main Routine * **************************************************************************** org Table_start * * Set up table of output compare values in RAM starting at $0060 * Freescale Semiconductor, Inc... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TIM08 Reference Manual — Rev. 1.0 150 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Applications Using the HC708XL36 DMA with the TIM Table Freescale Semiconductor, Inc... fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb fdb 0000 !1000 !2600 !4600 !5400 !6400 !8800 !10000 !11000 !13600 !15000 !16200 !17400 !18600 !19800 !21800 ;1st 16-bit entry ;2nd entry ;3rd entry ;4th entry ;5th entry ;6th entry ;7th entry ;8th entry ;9th entry ;10th entry ;11th entry ;12th entry ;13th entry ;14th entry ;15th entry ;16th entry * $PAGE **************************************************************************** * * * Program Initialization * * * * Code needed to initialize processor resources is placed here. * **************************************************************************** * org EPROM_Start ;start of HC708XL36 EPROM ($6E00) Start equ * ldhx #$450 ;load H:X with upper RAM boundary + 1. txs ;move stack pointer to upper RAM ; boundary. * * Initialization and configuration of DMA registers * ldhx #Table ;Write Source Base Address to D0SH:D0SL: sthx D0SH ; -this is the RAM table starting address. ldhx #TCH1H ;Write Destination Base Address to sthx D0DH ; D0DH:D0DL. This is Timer Channel 1 ; Output Compare Registers (TCH1H:TCH1L). mov #$89,D0C ;Configure DMA Channel 0 Control Reg: ; -increment source/ static destination. ; -word transfer mode. ; -Timer Channel 1 service request. mov #$10,DSC ;Configure DMA Status and Control Reg: ; -enable loop mode on DMA Channel 0. mov #$20,D0BL ;Load Block Length Register 0 with ; output compare table size (!32 bytes). mov #2,DC1 ;Configure DMA Control Register 1: ; -disable CPU interrupt on loop restart. ; -enable DMA Channel 0. * TIM08 Reference Manual — Rev. 1.0 MOTOROLA Applications For More Information On This Product, Go to: www.freescale.com 151 Freescale Semiconductor, Inc. Applications * * Initialization and configuration of Timer registers mov ldhx sthx ldhx sthx mov #$30,TSC #$5555 TCH1H #$6FFF TMODH #2,TDMA Freescale Semiconductor, Inc... ;Stop and reset Timer. ;Initialize output compare regs to ; generate first output compare. ;Configure Modulo Timer: ; -counter rollover at $6FFF cycles. ;Configure Timer DMA select register: ; -DMA service for Timer Channel 1 ; interrupts. mov #$54,TSC1 ;Configure Timer Channel 1 Status and ; Control Register: ; -enable output compare interrupts. ; -set up for output compare w/ toggle. ; -disable toggle on timer overflow. mov #0,TSC ;Start Timer. **************************************************************************** * * * Main Program Loop * * * **************************************************************************** * * Main equ * bra * ;stay here forever **************************************************************************** * * * Reset Vectors for Main Routine * * * **************************************************************************** org RESET fdb Start TIM08 Reference Manual — Rev. 1.0 152 Applications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Electrical Specifications Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Freescale Semiconductor, Inc... AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Introduction This section contains the electrical specifications and associated timing information for the TIM. AC Characteristics The following table provides information on the AC characteristics of the TIM. Table 11. AC Characteristics Characteristic Operating Frequency TIM Counter Clock Frequency TCLK Frequency Cycle time TIM Counter Period TCLK Pulse Width Timer Resolution (IC, OC, & PWM) 1The Symbol fOP fTCNT fTCLK tcyc tTCNT tTCLK tRESL Min 0 0 0 1251 1/fTCNT tcyc tcyc Max 81 fOP fOP/2 Unit MHz MHz MHz ns ns ns ns maximum operating speed (fOP) of the TIM is the maximum bus speed of the MCU. That speed depends on the voltage and temperature range. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Electrical Specifications For More Information On This Product, Go to: www.freescale.com 153 Freescale Semiconductor, Inc. Electrical Specifications Timing Specifications This section provides information on the timing relationships between the internal bus signals in the MCU. The CPU clock is referenced in the M68HC08 Central Processor Unit Reference Manual, order number CPU08RM/AD. The bus clocks, IT12 and IT23, are generated by the MCU clock generation module (CGM) and distributed to the MCU bus by the system integration module (SIM). The SIM also generates the internal address bus and internal data bus. All TIM timing is referenced to these internal bus signals from the SIM. The rise/fall timing and hysteresis for the timer channel/port pins is dependent on the port circuit, and is specified in MC68HC708XL36 Technical Summary, order number MC68HC708XL36/D. Freescale Semiconductor, Inc... 1 fBUS ns CPU CLOCK T1 T2 T3 T4 BUS CLOCK: IT12 IT23 INTERNAL ADDRESS BUS INTERNAL DATA BUS Figure 55. Internal Bus Signals TIM08 Reference Manual — Rev. 1.0 154 Electrical Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Freescale Semiconductor, Inc... Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .156 Timer DMA Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Timer Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .161 Timer Channel Status and Control Registers . . . . . . . . . . . . . . . . . .162 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Introduction This section contains an overview of the TIM registers. The following TIM registers are discussed in this section: timer status and control register (TSC), timer DMA select register (TDMA), timer counter registers (TCNTH:TCNTL), timer counter modulo registers (TMODH:TMODL), timer channel status and control registers (TSC0–TSC3), timer channel status and control registers (TSC0–TSC3), and timer channel registers (TCH0H/L–TCH3H/L). NOTE: The TIM can be implemented with two, four, six or eight channels. This manual will show the 4-channel version, as implemented in the MC68HC708XL36. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 155 Freescale Semiconductor, Inc. Memory Map and Registers Timer Status and Control Register TSC Read: Write: Reset: Bit 7 TOF 6 TOE 5 TSTOP 4 0 TRST 3 0 2 PS2 1 PS1 0 Bit 0 PS0 0 0 0 0 1 0 0 0 Figure 56. Timer Status and Control Register (TSC) Freescale Semiconductor, Inc... TOF — Timer overflow flag This clearable flag is set when the timer counter reaches the modulo value programmed in the timer modulo registers. Clear TOF by reading the timer status and control register when TOF is set and then writing a 0 to TOF. If another timer overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to this bit has no effect. Reset clears the TOF bit. 1 = Timer counter has reached modulo value. 0 = Timer counter has not reached modulo value. TOE — Timer overflow enable This read/write bit enables timer overflow interrupts when the TOF bit becomes set. Reset clears the TOE bit. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled TSTOP — Timer stop This read/write bit stops the timer counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the timer counter until the TIM is enabled. 1 = Timer counter stopped 0 = Timer counter active To preserve the correct timing relationship, TSTOP stops the input clock to the prescaler. The relationship cannot be preserved when using the external TCLK as the timer clock. See Figure 13 for details on the timing of the TSTOP function. TIM08 Reference Manual — Rev. 1.0 156 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Status and Control Register NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — Timer reset Setting this write-only bit resets the timer counter and the timer prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the timer counter is reset, and always reads zero. Reset clears the TRST bit. 1 = Prescaler and timer counter cleared 0 = No effect See Figure 14 for details on the timing of the TRST function. Freescale Semiconductor, Inc... NOTE: Setting the TSTOP and TRST bits simultaneously stops the timer counter at a value of $0000. Bit 3 — Not used; always reads 0. PS2–PS0 — Prescaler bits These read/write bits select the bus clock, one of the six prescaler outputs, or the TCLK pin as the input to the timer counter. Table 12 shows the prescaler selection encoding, including the TIM clock source, and the function of the TCLK pin. Reset clears the PS2–PS0 bits. Table 12. Prescaler Selection PS2: PS1: PS0 000 001 010 011 100 101 110 111 TIM Clock Source Bus Clock Bus Clock ÷ 2 Bus Clock ÷ 4 Bus Clock ÷ 8 Bus Clock ÷ 16 Bus Clock ÷ 32 Bus Clock ÷ 64 TCLK PORT/TCLK Function PORT PORT PORT PORT PORT PORT PORT TCLK NOTE: Stop the TIM before changing the prescaler output. Before writing to the prescaler select bits (PS2–PS0), set the timer stop bit (TSTOP). TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 157 Freescale Semiconductor, Inc. Memory Map and Registers NOTE: Changing the prescaler control bits while the prescaler is running may cause an extra count if the input clock previously selected was a logic level 0 and the new input clock logic level is 1. See Special Modes for information on stopping the prescaler. Timer DMA Select Register Freescale Semiconductor, Inc... NOTE: This register is available only on microcontrollers with a DMA module. If no DMA module is included, do not enable the bits described in Figure 57. If those bits are enabled, no CPU interrupts for that channel will be generated or serviced. The timer DMA register selects either the CPU or the DMA module to service TIM interrupts. These bits are cleared on reset, selecting the CPU to process interrupts. TDMA Read: Write: Reset: Bit 7 0 6 0 5 0 4 0 3 DMA3S 2 DMA2S 0 1 DMA1S 0 Bit 0 DMA0S 0 0 0 0 0 0 Figure 57. Timer DMA Select Register (TDMA) DMA3S — DMA channel 3 select This read/write bit enables the DMA to process TIM interrupts on timer channel 3. Reset clears the DMA3S bit. 1 = Timer channel 3 generates DMA service requests. 0 = Timer channel 3 generates CPU interrupt requests. DMA2S — DMA channel 2 select This read/write bit enables the DMA to process TIM interrupts on timer channel 2. Reset clears the DMA2S bit. 1 = Timer channel 2 generates DMA service requests. 0 = Timer channel 2 generates CPU interrupt requests. TIM08 Reference Manual — Rev. 1.0 158 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer DMA Select Register DMA1S — DMA channel 1 select This read/write bit enables the DMA to process TIM interrupts on timer channel 1. Reset clears the DMA1S bit. 1 = Timer channel 1 generates DMA service requests. 0 = Timer channel 1 generates CPU interrupt requests. DMA0S — DMA channel 0 select This read/write bit enables the DMA to process TIM interrupts on timer channel 0. Reset clears the DMA0S bit. 1 = Timer channel 0 generates DMA service requests. 0 = Timer channel 0 generates CPU interrupt requests. Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 159 Freescale Semiconductor, Inc. Memory Map and Registers Timer Counter Registers These two read-only timer counter registers (TCNT) contain the high and low bytes of the value in the timer counter. The counter value can be read at any time with user software without affecting its value. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL). Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. The LDHX instruction can be used to read a value from TCNT. The counter is set to $0000 on reset or when the timer reset bit (TRST) is set. Freescale Semiconductor, Inc... TCNTH Read: Write: Reset: Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 8 0 0 0 0 0 0 0 0 TCNTL Read: Write: Reset: Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 0 0 0 0 0 0 0 0 Figure 58. Timer Counter Registers (TCNTH:TCNTL) TIM08 Reference Manual — Rev. 1.0 160 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Counter Modulo Registers Timer Counter Modulo Registers These two read/write timer counter modulo registers (TMOD) contain the high and low bytes of the modulo value for the timer counter. When the timer counter reaches the modulo value, the TOF flag is automatically set by hardware, and the timer counter resumes counting from $0000 at the next clock. The overflow flag (TOF) and overflow interrupts are inhibited after a write to the high byte (TMODH) until the low byte (TMODL) is written. The STHX instruction can be used to write values to TMOD, and the LDHX instruction can be used to read values from TMOD. Reset sets the timer counter modulo registers to $FFFF, enabling the modulo counter to act as a free-running counter. TMODH Read: Write: Reset: TMODL Read: Write: Reset: Bit 15 Bit 15 1 Bit 7 Bit 7 1 14 14 1 6 6 1 13 13 1 5 5 1 12 12 1 4 4 1 11 11 1 3 3 1 10 10 1 2 2 1 9 9 1 1 1 1 Bit 8 Bit 8 1 Bit 0 Bit 0 1 Freescale Semiconductor, Inc... Figure 59. Timer Counter Modulo Registers (TMODH:TMODL) NOTE: NOTE: If TMODH:TMODL is set to $0000, a TOF is generated on the first cycle in which the match occurs, but not subsequently. Stop and reset the timer counter before writing to the timer counter modulo registers. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 161 Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Status and Control Registers The timer channel status and control registers are 8-bit read/write registers. These registers are used to configure the timer channel to perform input capture, output compare, or PWM functions. The state of these registers is reset to $00. Each of the timer channel status and control registers does the following: • Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, unbuffered output compare, buffered output compare, unbuffered PWM, or buffered PWM operation Selects, high, low, or toggling output on output compare or PWM match Selects rising, falling, or any edge as the active input capture trigger Selects output toggling on timer overflow Selects 100% PWM duty cycle Freescale Semiconductor, Inc... • • • • • • TIM08 Reference Manual — Rev. 1.0 162 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Status and Control Registers TSC0 Read: Write: Reset: Bit 7 CH0F 6 CH0IE 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0 0 0 0 TSC1 Read: Bit 7 CH1F 6 CH1IE 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0 Freescale Semiconductor, Inc... Write: Reset: 0 0 0 TSC2 Read: Write: Reset: Bit 7 CH2F 6 CH2IE 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 Bit 0 CH2MAX 0 0 0 0 TSC3 Read: Write: Reset: Bit 7 CH3F 6 CH3IE 5 0 0 4 MS3A 0 3 ELS3B 0 2 ELS3A 0 1 TOV3 0 Bit 0 CH3MAX 0 0 0 0 Figure 60. Timer Channel Status and Control Registers (TSC0–TSC3) CHxF— Channel x flag When channel x is an input capture channel, this clearable bit is set when an active edge occurs on the channel x pin. When channel x is an output compare or PWM channel, CHxF is set when the value in the timer counter registers matches the value in the timer channel x registers. When CPU interrupts are enabled (CHxIE:DMAxS = 1:0), clear CHxF by reading the channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 163 Freescale Semiconductor, Inc. Memory Map and Registers clearing sequence is complete, then writing zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. When DMA service requests are available and enabled (CHxIE:DMAxS = 1:1), clear CHxF by reading or writing to the low byte of the channel register (TCHxL). DMA service requests may not be used with buffered OC/PWM functions. Writing a 1 to this bit has no effect. Reset clears the CHxF bit. 1 = Input capture or OC/PWM match on channel x 0 = No input capture or OC/PWM match on channel x CHxIE — Channel x interrupt enable This read/write bit enables channel x interrupts. In microcontrollers with a DMA module, the DMAxS bit in the timer DMA select register selects channel x CPU interrupts or DMA service requests for the input capture or unbuffered OC/PWM modes. DMA service requests cannot be used with buffered OC/PWM mode, therefore the DMAxS bit in the timer DMA select register should be cleared to select channel x CPU interrupts. Reset clears the CHxIE bit. 1 = Channel x interrupts enabled 0 = Channel x interrupts disabled MSxB — Mode select bit B MSxB exists only in the channel 0 and channel 2 status and control registers, TSC0 and TSC2. This read/write bit selects buffered OC or buffered PWM operation. Setting MS0B disables the channel 1 status and control register, and reverts TCH1 to general-purpose I/O. Setting MS2B disables the channel 3 status and control register, and reverts TCH3 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered OC/PWM mode enabled 0 = Buffered OC/PWM mode disabled Freescale Semiconductor, Inc... 164 TIM08 Reference Manual — Rev. 1.0 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Status and Control Registers MSxA — Mode select bit A This bit has different functions, depending on the state of ELSxB and ELSxA. When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. To select the level of your initial output, write the appropriate value to MSxA while ELSxB:A = 00. Then configure all bits in the TSCx as required for your application. 1 = Initial output level low 0 = Initial output level high Freescale Semiconductor, Inc... When ELSxB:A ≠ 00, this read/write bit selects input capture mode or unbuffered OC/PWM mode, as shown in Table 13. MS0A and MS1A are active only when MS0B = 0. MS2A and MS3A are active only when MS2B = 0. Reset clears the MSxA bit. 1 = Unbuffered OC/PWM operation 0 = Input capture operation NOTE: Stop and reset the TIM before changing a channel function. Before writing to the mode select bits (MSxB and MSxA), set the timer stop and timer reset bits (TSTOP and TRST) in the TSC register. ELSxB and ELSxA — Edge/level select bits When channel x is an input capture channel, these read/write bits control the active edge sensing logic on channel x. When channel x is an output compare or PWM channel, ELSxB and ELSxA control the channel x output behavior when an output compare or pulse width match occurs. When ELSxB and ELSxA are both clear, channel x is not connected to the port, and pin TCHx is available as a general-purpose I/O pin. Table 13 shows the configuration selected by ELSxB and ELSxA. Reset clears the ELSxB and ELSxA bits. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 165 Freescale Semiconductor, Inc. Memory Map and Registers Table 13. Mode, Edge, and Level Selection MSxB: MSxA X0 X1 00 00 ELSxB: ELSxA 00 00 00 01 10 11 00 01 10 11 00 01 10 11 Mode Output Preset Output Preset Input Capture Input Capture Input Capture Input Capture Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Unbuffered OC/PWM Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Buffered OC/PWM Configuration Set initial output level high Set initial output level low TCHx Pin under port control; set initial output level high Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge TCHx Pin under port control; set initial output level low Toggle Output on OC/PWM Match Clear Output on OC/PWM Match Set Output on OC/PWM Match TCHx Pin under port control; set initial output level Toggle Output on OC/PWM Match Clear Output on OC/PWM Match Set Output on OC/PWM Match Freescale Semiconductor, Inc... 00 00 01 01 01 01 1X 1X 1X 1X NOTE: Before enabling the channel register for input capture, make sure that the PTE/TCHx pin is stable for a minimum of two bus clocks. TOVx — Toggle on overflow When channel x is a buffered or unbuffered OC/PWM channel, this read/write bit controls the behavior of the channel x output when the timer counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on timer counter overflow. 0 = Channel x pin does not toggle on timer counter overflow. NOTE: When TOVx is set, a timer counter overflow takes precedence over a channel x output compare if both occur at the same time. TIM08 Reference Manual — Rev. 1.0 166 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Status and Control Registers CHxMAX — PWM 100% duty cycle This read/write bit forces the duty cycle of buffered and unbuffered OC/PWM signals to 100%. As Figure 61 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. CHxMAX affects only the logic level of the channel x pin; output compares or pulse width matches can continue to occur and set the channel x flag. Reset clears the CHxMAX bit. Freescale Semiconductor, Inc... PERIOD TIMER OVERFLOW TCHx OUTPUT COMPARE CHxMAX Figure 61. CHxMAX Latency TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 167 Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Registers These read/write registers are used as the 16-bit input capture register latch for input capture functions, and as the 16-bit compare register for output compare and PWM functions. For input capture functions, these registers latch the value of TCNT when a specified transition is detected on the corresponding input capture pin. For output compare and PWM functions, these registers contain the output compare value for the output compare function or the pulse width match value for the PWM function. The state of the channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the channel register (TCHxH) inhibits input captures until the low byte (TCHxL) is read. This prevents another input capture from overwriting the TCHxH:TCHxL registers before the previous value has been read. An overwrite of TCHxH:TCHxL will occur if another IC is received before the TCHxH is read. The LDHX instruction may be used to read these registers. Writing to the timer channel registers will overwrite any input capture data. In unbuffered output compare/PWM modes, output compares/pulse width matches are inhibited between writes to TCHxH and TCHxL. This prevents another output compare/pulse width match from occurring until the new output compare/pulse width value is written. In buffered output compare/PWM modes, output compares/pulse width matches are inhibited between writes to TCHxH and TCHxL of the active channel. This prevents another output compare/pulse width match from occurring until the new pulse width value is written. Output compares are allowed between writes to TCHxH and TCHxL of the inactive channel. The sthx instruction can be used to write to TCHxH:L. If a timer channel register is not used for an input capture, output compare, or PWM function, it can be used as a storage location. Freescale Semiconductor, Inc... 168 TIM08 Reference Manual — Rev. 1.0 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Memory Map and Registers Timer Channel Registers TCH0H Read: Bit 15 Bit 15 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 Write: Reset: TCH0L Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 15 Bit 15 Write: Reset: TCH1L Read: Bit 7 Write: Reset: TCH2H Read: Bit 15 Write: Reset: TCH2L Read: Bit 7 Write: Reset: TCH3H Read: Bit 15 Write: Reset: TCH3L Read: Bit 7 Write: Reset: Indeterminate after Reset 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Bit 15 14 13 Indeterminate after Reset 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 14 14 13 13 12 12 11 11 10 10 9 9 Bit 8 Bit 8 6 5 4 3 2 1 Bit 0 Bit 7 6 5 Indeterminate after Reset 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... TCH1H Read: Figure 62. Timer Channel Registers (TCH0H/L–TCH3H/L) TIM08 Reference Manual — Rev. 1.0 MOTOROLA Memory Map and Registers For More Information On This Product, Go to: www.freescale.com 169 Freescale Semiconductor, Inc. Memory Map and Registers Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 170 Memory Map and Registers For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin Summary Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Freescale Semiconductor, Inc... TIM Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 TIM Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Introduction This section summarizes the TIM pins, the pin configuration control bits, and the data on the external pins. TIM Pin Functions The following table summarizes the specific TIM pin functions. Table 14. Pin Functions Pin GPI GPO ICx OCx TCLK Pin Function General-purpose input General-purpose output TIM input capture TIM output compare/PWM match Pin is used as external clock input. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Pin Summary For More Information On This Product, Go to: www.freescale.com 171 Freescale Semiconductor, Inc. Pin Summary TIM Pin Summary The following tables summarize the individual TIM pins. Table 15. TCH0 and TCH2 Pins Function GPI GPO MSxB: MSxA 00 00 00 00 00 01 01 01 01 01 1X 1X 1X 1X 1X ELSxB: ELSxA 00 00 01 10 11 00 00 01 10 11 00 00 01 10 11 DDRx 0 1 X X X 0 1 X X X 0 1 X X X Pin Direction Input Output Input Input Input Input Output Output Output Output Input Output Output Output Output Configuration PORT Pin PORT Pin ICx on Rising Edge Only ICx on Falling Edge Only ICx on Rising or Falling Edge PORT Pin PORT Pin Toggle Output on OCx Clear Output on OCx Set Output on OCx PORT Pin PORT Pin Toggle Output on OCx Clear Output on OCx Set Output on OCx Freescale Semiconductor, Inc... ICx ICx ICx GPI GPO OCx OCx OCx GPI GPO OCx OCx OCx TIM08 Reference Manual — Rev. 1.0 172 Pin Summary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin Summary TIM Pin Summary Table 16. TCH1 and TC H3 Pins Function GPI GPO ICx ICx MS0B: MS2B 0 0 0 0 0 0 0 0 0 0 1 1 MS1A: MS3A 0 0 0 0 0 1 1 1 1 1 X X ELS1B: ELS1A Pin ELS3B: DDREx Direction ELS3A 00 00 01 10 11 00 00 01 10 11 XX XX 0 1 X X X 0 1 X X X 0 1 Input Output Input Input Input Input Output Output Output Output Input Output Configuration PORT Pin PORT Pin Rising Edge Only Falling Edge Only Rising or Falling Edge PORT Pin PORT Pin Toggle Output Clear Output Set Output PORT Pin PORT Pin Freescale Semiconductor, Inc... ICx GPI GPO OCx OCx OCx GPI GPO Table 17. TCLK Pin Function GPI GPI GPI GPO GPO GPO TCLK PS2: PS1: PS0 0XX X0X XX0 0XX X0X XX0 111 DDRE3 0 0 0 1 1 1 X Pin Direction Input Input Input Output Output Output Input Configuration PORT Pin PORT Pin PORT Pin PORT Pin PORT Pin PORT Pin TIM Clock Input TIM08 Reference Manual — Rev. 1.0 MOTOROLA Pin Summary For More Information On This Product, Go to: www.freescale.com 173 Freescale Semiconductor, Inc. Pin Summary Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 174 Pin Summary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Glossary $xxxx — The digits following the “$” are in hexadecimal format. #xxxx — The digits following the “#” indicate an immediate operand. Freescale Semiconductor, Inc... A — Accumulator. See “accumulator.” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and nonarithmetic operations. address bus — The set of signals used to select a specific memory location so that the CPU can write information into the memory location or read its contents. addressing mode — The way that the CPU obtains (addresses) the information needed to complete an instruction. The M68HC08 CPU has 16 addressing modes. algorithm — A set of specific procedures by which a solution is obtained in a finite number of steps, often used in numerical calculations. ALU — Arithmetic logic unit. See “arithmetic logic unit.” arithmetic logic unit (ALU) — The portion of the CPU of a computer where mathematical and logical operations take place. Other circuitry decodes each instruction and configures the ALU to perform the necessary arithmetic or logical operations at each step of an instruction. assembly language — A method used by programmers for representing machine instructions (binary data) in a more convenient form. Each machine instruction is given a simple, short name, called a mnemonic (or memory aid), which has a TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 175 Freescale Semiconductor, Inc. Glossary one-to-one correspondence with the machine instruction. The mnemonics are translated into an object code program which a microcontroller can use. ASCII — American Standard Code for Information Interchange. A widely accepted correlation between alphabetic and numeric characters and specific 7-bit binary numbers. asynchronous — Refers to circuitry and operations without common reference signals. Freescale Semiconductor, Inc... BCD — Binary-coded decimal. See “binary-coded decimal.” binary — The binary number system using 2 as its base and using only the digits 0 and 1. Binary is the numbering system used by computers because any quantity can be represented by a series of ones and zeros. Electrically, these ones and zeros are represented by voltage levels of approximately Vdd (input) and Vss (ground), respectively. binary-coded decimal (BCD) — A notation that uses binary values to represent decimal quantities. Each BCD digit uses 4 binary bits. Six of the possible 16 binary combinations are considered illegal. bit — A single binary digit. A bit can hold a single value of zero or one. Boolean — A mathematical system of representing logic through a series of algebraic equations that can only be true or false, using operators such as AND, OR, and NOT. branch instructions — Computer instructions that cause the CPU to continue processing at a memory location other than the next sequential address. Most branch instructions are conditional. That is, the CPU will continue to the next sequential address (no branch) if a condition is false, or continue to some other address (branch) if the condition is true. buffered — Utilizes a second storage register to prevent overwriting of valid data. bus — A collection of logic signals used to transfer information. TIM08 Reference Manual — Rev. 1.0 176 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Glossary bus clocks — There are two bus clocks, IT12 and IT23. These clocks are generated by the CGM and distributed throughout the MCU by the SIM. The frequency of the bus clocks, or operating frequency, is fop. While the frequency of these two clocks is the same, the phase is different. See Figure 55. Internal Bus Signals. byte — A set of exactly eight binary bits. C — Abbreviation for carry/borrow in the condition code register of the CPU08. The CPU08 sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the C flag (as in bit test and branch instructions and shifts and rotates). CCR — Abbreviation for condition code register in the CPU08. See “condition code register.” central processor unit (CPU) — The primary functioning unit of any computer system. The CPU controls the execution of instructions. CGM — Clock generation module. See “clock generation module.” checksum — A value that results from adding a series of binary numbers. When exchanging information between computers, a checksum gives an indication about the integrity of the data transfer. If values were transferred incorrectly, it is unlikely that the checksum would match the value that was expected. clear — To establish logic zero state on a bit or bits; the opposite of “set.” clock — A square wave signal used to sequence events in a computer. Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 177 Freescale Semiconductor, Inc. Glossary clock generation module (CGM) — A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit. comparator — A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits (flags) that indicate the results of the instruction just executed. control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. counter clock — The input clock to the TIM counter. This clock is an output of the prescaler sub-module. The frequency of the counter clock is ftcnt, and the period is ttcnt. CPU — Central processor unit. See “central processor unit.” CPU08 — The central processor unit of the M68HC08 Family. CPU cycles — A CPU clock cycle is one period of the internal bus-rate clock, fop, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. Freescale Semiconductor, Inc... 178 TIM08 Reference Manual — Rev. 1.0 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Glossary Freescale Semiconductor, Inc... CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: – A (8-bit accumulator) – H:X (16-bit accumulator) – SP (16-bit stack pointer) – PC (16-bit program counter) – CCR (condition code register containing the V, H, I, N, Z, and C bits) cycles — See “CPU cycles.” cycle time — The period of the operating frequency: tcyc=1/fop. data bus — A set of signals used to convey binary information from a CPU to a memory location or from a memory location to a CPU. data direction register (DDR) — A register which determines the function (input or output) of each pin in a data port. DDR — Data direction register. See “data direction register.” decimal — Base ten numbering system that uses the digits zero through nine. digital-to-analog converter (DAC) — A particular type of circuitry that changes digital information into analog information such as voltage or current. direct memory access (DMA) — One of a number of modules that handle a variety of control functions in the modular M68HC08 Family. The DMA can perform interrupt-driven and software-initiated data transfers between any two CPU-addressable locations. Each DMA channel can independently transfer data between any addresses in the memory map. DMA transfers reduce CPU overhead required for data movement interrupts. direct page — The first 256 bytes of memory ($0000–$00FF); also called page 0. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 179 Freescale Semiconductor, Inc. Glossary DMA — Direct memory access. See “direct memory access.” duty cycle — A ratio of the amount of time the signal is on versus the time it is off. It is usually represented by a percentage. effective address (EA) — The address where an instruction operand is located. The addressing mode of an instruction determines how the CPU calculates the effective address of the operand. EPROM — Erasable, Programmable, Read-Only Memory. A non-volatile type of memory that can be erased by exposure to an ultraviolet light source. execution unit (EU) — One of the two major units of the CPU containing the arithmetic logic unit (ALU), CPU registers, and bus interface. The outputs of the control unit drive the execution unit. free-running counter — A device which counts from zero to a pre-determined number, then rolls over to zero and begins counting again. H — Abbreviation for the upper byte of the 16-bit index register (H:X) in the CPU08. H — Abbreviation for “half-carry” in the condition code register of the CPU08. This bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction uses the state of the H and C flags to determine the appropriate correction factor. hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. One hexadecimal digit can exactly represent a 4-bit binary value. high order — The leftmost digit(s) of a number. H:X — Abbreviation for the 16-bit index register in the CPU08. See “index register.” TIM08 Reference Manual — Rev. 1.0 180 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary I — Abbreviation for “interrupt mask bit” in the condition code register of the CPU08. When I is set, all interrupts are disabled. When I is cleared, interrupts are enabled. index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location. Freescale Semiconductor, Inc... input/output (I/O) — Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. instruction set — The instruction set of a CPU is the set of all operations that the CPU can perform. An instruction set is often represented with a set of shorthand mnemonics, such as LDA, meaning “load accumulator (A).” Another representation of an instruction set is with a set of opcodes that are recognized by the CPU. interrupt — Provide a means to temporarily suspend normal program execution so that the CPU is freed to service sets of instructions in response to requests (interrupts) from peripheral devices. Normal program execution can be resumed later from its original point of departure. The CPU08 can process up to 128 separate interrupt sources, including a software interrupt (SWI). interrupt service routine — An I/O software routine servicing a specific interrupt. I/O — Input/output. See “input/output.” IRQ — Interrupt request. The overline indicates an active-low signal. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 181 Freescale Semiconductor, Inc. Glossary least significant bit (LSB) — The rightmost digit of a binary value. logic one — A voltage level approximately equal to the input power voltage (VDD). logic zero — A voltage level approximately equal to the ground voltage (VSS). low order — The rightmost digit(s) of a number. LS — Least significant. Freescale Semiconductor, Inc... LSB — Least significant bit. See “least significant bit.” M68HC08 — A Motorola family of 8-bit MCUs. machine codes — The binary codes processed by the CPU as instructions. Machine code includes both opcodes and operand data. MCU — Microcontroller unit. See “microcontroller.” memory location — In the M68HC08 each memory location holds one byte of data and has a unique address. To store information into a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus. memory map — A pictorial representation of all memory locations in a computer system. microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit. TIM08 Reference Manual — Rev. 1.0 182 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Glossary mnemonic — Three to five letters that represent a computer operation. For example, the mnemonic form of the “load accumulator” instruction is LDA. modulo counter — A device capable of being programmed so that it counts to any number from zero to its maximum possible modulus. most significant bit (MSB) — The leftmost digit of a binary value. Freescale Semiconductor, Inc... MS — Abbreviation for “most significant.” MSB — Most significant bit. See “most significant bit.” multiplexer (mux) — A digital device that can select one of a number of inputs and pass the logic level of that input on to the output. N — Abbreviation for “negative,” a bit in the condition code register of the CPU08. The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble — Half a byte; 4 bits. object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. one — A logic high level, a voltage level approximately equal to the input power voltage (VDD). one’s complement — An infrequently used form of signed binary numbers. Negative numbers are simply the complement of their positive counterparts. One’s complement is the result of a bit by bit complement of a binary word: all ones are changed to zeros and all zeros changed to ones. One’s complement is two’s complement without the increment. opcode — A binary code that instructs the CPU to do a specific operation in a specific way. TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 183 Freescale Semiconductor, Inc. Glossary operand — The fundamental quantity on which a mathematical operation is performed. Usually a statement consists of an operator and an operand. The operator may indicate an add instruction; the operand therefore will indicate what is to be added. oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. Freescale Semiconductor, Inc... overflow — This condition occurs when the modulo counter reaches its modulo value and rolls over to zero. page 0 — The first 256 bytes of memory ($0000–$00FF). Also called direct page. PC — Program counter. See “program counter.” pointer — Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore “points” to the operand. port — A collection of individual I/O signals. prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program — A set of computer instructions that cause a computer to perform a desired operation or operations. programming model — The registers of a particular CPU. program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use. TIM08 Reference Manual — Rev. 1.0 184 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Glossary pull — The act of reading a value from the stack. In the M68HC08, a value is pulled by the following sequence of operations. First, the stack pointer register is incremented so that it points to the last value saved on the stack. Next, the value at the address contained in the stack pointer register is read into the CPU. pulse-width — The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) — Controlled variation (modulation) of a pulse width, with a constant frequency. PWM period — The time required for one complete cycle of a PWM waveform. push — The act of storing a value at the address contained in the stack pointer register and then decrementing the stack pointer so that it points to the next available stack location. RAM — Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit — A circuit consisting of capacitors and resistors having a defined time constant. read — To transfer the contents of a memory location to the CPU. registers — Memory locations wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: – A (8-bit accumulator) – (H:X) (16-bit accumulator) – SP (16-bit stack pointer) – PC (16-bit program counter) – CCR (condition code register containing the V, H, I, N, Z, and C bits) Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 185 Freescale Semiconductor, Inc. Glossary Memory locations that hold status and control information for on-chip peripherals are called input/output (I/O) and control registers. reset — Reset is used to force a computer system to a known starting point and to force on-chip peripherals to known starting conditions. ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. servo loop — In a servo amplifier, the entire closed loop formed by feedback from output to input. In a position servo, the output position is compared to a command signal at the input. set — To establish a logic one state on a bit or bits; opposite of “clear.” signal groups — Groups of electronic signals related by function. signed — A form of binary number representation accommodating both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally zero for positive and one for negative, and the other seven bits indicate the magnitude. SIM — System integration module. See “system integration module.” software interrupt (SWI) — An instruction that will cause an interrupt and its associated vector fetch. SP — Stack pointer. See “stack pointer.” stack — A mechanism for temporarily saving CPU register values during interrupts and subroutines. The CPU maintains this structure with the stack pointer (SP) register, which contains the address of the next available (empty) storage location on the stack. When a subroutine is called, the CPU pushes (stores) the low-order and high-order bytes of the return address on the stack before starting the subroutine instructions. When the subroutine is done, a return from subroutine (RTS) instruction TIM08 Reference Manual — Rev. 1.0 186 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary causes the CPU to recover the return address from the stack and continue processing where it left off before the subroutine. Interrupts work in the same way except that all CPU registers are saved on the stack instead of just the program counter. The H register is not pushed on the stack during an interrupt. stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available (empty) storage on the stack. status bit — One bit of a register used to store information about the status of the module. subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. SWI — Software interrupt. See “software interrupt.” synchronous — Refers to two or more things made to happen simultaneously in a system by means of a common reference signal. system integration module (SIM) — One of a number of modules that handle a variety of control functions in the modular M68HC08 Family. The SIM controls mode of operation, resets and interrupts, and system clock generation. TIM — Timer Interface Module. timer — A module used to relate events in a system to a point in time. toggle — To change the state of an output from a logic zero to a logic one or from a logic one to a logic zero. Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 MOTOROLA Glossary For More Information On This Product, Go to: www.freescale.com 187 Freescale Semiconductor, Inc. Glossary two’s complement — A means of performing binary subtraction using addition techniques. The most significant bit of a two’s complement number indicates the sign of the number (1 indicates negative). The two’s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered — Utilizes only one register for data; new data overwrites current data. Freescale Semiconductor, Inc... unsigned — Refers to a binary number representation in which all numbers are assumed positive. With signed binary, the most significant bit is used to indicate whether the number is positive or negative, normally zero for positive and one for negative, and the other seven bits indicating the magnitude. variable — A value that changes during the course of executing a program. waveform — A graphical representation in which the amplitude of a wave is plotted against time. word — Two bytes or 16 bits, treated as a unit. write — The transfer of a byte of data from the CPU to a memory location. X — Abbreviation for the lower byte of the index register (H:X) in the CPU08. Z — Abbreviation for zero, a bit in the condition code register of the CPU08. The CPU08 sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. zero — A logic low level, a voltage level approximately equal to the ground voltage (Vss). TIM08 Reference Manual — Rev. 1.0 188 Glossary For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Index A AC characteristics .............................................................................153 Applications general TIM08 information ..........................................................121 input capture ...............................................................................121 output compare ...........................................................................123 PWM ...........................................................................................125 PWM controlled RC digital to analog converter ..........................131 Servo loop motor control .............................................................139 using the HC708XL36 DMA with the TIM08 ...............................144 Auxiliary Timer Clock Input (PTE3/TCLK) ..........................................38 Freescale Semiconductor, Inc... B Buffered output compare diagram .........................................................................................74 functions ........................................................................................72 mode and level selection ...............................................................77 Buffered PWM diagram .........................................................................................93 functions ........................................................................................90 mode and level selection ...............................................................96 C Capture/compare unit buffered compare functions ...........................................................72 buffered output compare mode and level selection ......................77 buffered pulse width modulation functions ....................................90 input capture functions ..................................................................57 input capture mode and edge selection ........................................62 input capture timing diagram .........................................................58 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Index For More Information On This Product, Go to: www.freescale.com 189 Freescale Semiconductor, Inc. Index timer channel and control registers ...............................................75 timer channel registers ................................................63, 70, 71, 78 timer channel status and control registers ......60, 67, 75, 83, 84, 94 unbuffered output compare functions ............................................65 unbuffered output compare mode and level selection ..................70 unbuffered output compare timing diagram ..................................66 unbuffered pulse width modulation functions ................................80 CHxMAX latency ................................................................................97 CPU interrupts ..................................................................................104 Freescale Semiconductor, Inc... D DMA service requests ......................................................................111 E Edge selection and input capture mode .............................................62 Electrical specification AC characteristics .......................................................................153 internal bus signals .....................................................................154 timing specifications ....................................................................154 G General purpose I/O description .....................................................................................37 I I/O .......................................................................................................37 IC ........................................................................................................57 Input capture description ...................................................................................121 functions ........................................................................................57 mode and edge selection ..............................................................62 pins ................................................................................................37 timing ...................................................................................105, 111 timing diagram ...............................................................................58 TIM08 Reference Manual — Rev. 1.0 190 Index For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Index Input capture/output compare pins .....................................................36 Internal bus signals ...........................................................................154 Interrupts CPU interrupts .............................................................................104 input capture timing .............................................................105, 111 output compare/PWM timing ...............................................109, 113 TIM interrupt priority ....................................................................104 timer DMA select register (TDMA) ..............................................102 timer overflow timing ...................................................................105 Freescale Semiconductor, Inc... L LDHX ..................................................................................................54 M Memory map and registers timer channel registers ................................................................168 timer channel status and control registers ..................................162 timer counter modulo registers ....................................................161 timer counter registers ................................................................160 timer DMA select register (TDMA) ..............................................158 timer status and control register (TSC) .......................................156 Modulo counter simplified block diagram ................................................................48 timer counter .................................................................................47 timer counter modulo registers ......................................................54 timer counter registers ..................................................................53 TRST timing ..................................................................................52 TSTOP timing ................................................................................50 Monitor mode ....................................................................................117 O Output compare ................................................................................123 Output compare pins ..........................................................................37 Output compare/input capture pins ....................................................36 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Index For More Information On This Product, Go to: www.freescale.com 191 Freescale Semiconductor, Inc. Index Output compare/PWM timing ...........................................................109 Output compares buffered .........................................................................................28 unbuffered .....................................................................................28 P Pin functions .....................................................................................171 Pin summary TCH0 ...........................................................................................172 TCH1 ...........................................................................................173 TCH2 ...........................................................................................172 TCH3 ...........................................................................................173 TCLK ...........................................................................................173 TIM pin functions .................................................................171, 172 Pins .....................................................................................................37 Prescaler TCLK timing ..................................................................................41 timer status and control register (TSC) .........................................41 TRST timing ..................................................................................44 TSTOP timing ................................................................................42 PTE3/TCLK ........................................................................................38 Pulse width modulation .......................................................................30 PWM application ...................................................................................125 block diagram ................................................................................31 buffered signal generation .............................................................33 controlled RC digital to analog converter ....................................131 output pins .....................................................................................37 period and pulse width ............................................................80, 90 unbuffered functions ......................................................................80 unbuffered signal generation .........................................................32 PWM signal generation buffered .........................................................................................33 unbuffered .....................................................................................32 Freescale Semiconductor, Inc... 192 TIM08 Reference Manual — Rev. 1.0 Index For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Index R Registers overview ......................................................................................155 TSCx .............................................................................................37 S Service requests DMA ............................................................................................111 Freescale Semiconductor, Inc... Servo loop motor control ..................................................................139 Signal descriptions introduction ....................................................................................35 signal groups .................................................................................36 Special modes monitor mode ..............................................................................117 stop mode ...................................................................................116 wait mode ....................................................................................116 STHX ..................................................................................................54 Stop mode ........................................................................................116 T TCH0 ................................................................................................172 TCH0H/L-TCH3H/L ..........................................................63, 64, 70, 78 TCH1 ................................................................................................173 TCH2 ................................................................................................172 TCH3 ................................................................................................173 TCHxH L .............................................................................................59 TCHxH TCHxL ....................................................................................37 TCHxH/L .............................................................................................57 TCHxL ................................................................................................61 TCLK ................................................................................................173 TCNT ......................................................................................47, 48, 53 TCNTH ...............................................................................................53 TCNTH TCNTL ...................................................................................20 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Index For More Information On This Product, Go to: www.freescale.com 193 Freescale Semiconductor, Inc. Index TCNTL ................................................................................................53 TDMA .......................................................................................102, 158 TIM interrupt priority .........................................................................104 TIM pin functions ..............................................................................171 TIM08 block diagram ................................................................................22 buffered output compare simplified block diagram ........................29 buffered output compares .............................................................28 buffered PWM signal generation ...................................................33 buffered PWM simplified block diagram ........................................34 features .........................................................................................24 input capture concepts ..................................................................25 input capture simplified block diagram ..........................................25 output compare concepts ..............................................................26 output compare simplified block diagram ......................................27 pulse-width modulation block diagram ..........................................31 pulse-width modulation concepts ..................................................30 PWM .............................................................................................30 PWM block diagram ......................................................................31 submodules ...................................................................................20 unbuffered output compares .........................................................28 unbuffered PWM signal generation ...............................................32 Timer channel registers (TCH0H/L-TCH3H/L) buffered OC ...................................................................................78 description .............................................................................63, 168 unbuffered OC ...............................................................................70 Timer channel status and control registers TSC0-TSC3 buffered OC ...................................................................................75 buffered PWM ...............................................................................94 description .............................................................................60, 162 unbuffered OC ...............................................................................67 unbuffered PWM ...........................................................................83 Timer counter .....................................................................................47 Timer counter modulo registers ..................................................54, 161 Timer counter registers ...............................................................53, 160 Timer DMA select register ................................................................102 TIM08 Reference Manual — Rev. 1.0 194 Index For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Index Timer DMA select register (TDMA) ..................................................158 Timer overflow timing .......................................................................105 Timer status and control register (TSC) ...............................41, 49, 156 Timing specifications ........................................................................154 TMOD ...........................................................................................48, 54 TMODH ..............................................................................................54 TMODH TMODL ...........................................................................20, 54 TMODL ...............................................................................................54 TOF ........................................................................................48, 49, 54 TRST ............................................................................................44, 51 TRST timing ........................................................................................52 TSC ................................................................................40, 41, 49, 156 TSC0 ..................................................................................................75 TSC0-TSC2 ........................................................................................94 TSC0-TSC3 ............................................................................60, 67, 83 TSC2 ..................................................................................................75 TSCx .............................................................................................37, 57 TSTOP ................................................................................................49 TSTOP timing ...............................................................................42, 50 Freescale Semiconductor, Inc... U Unbuffered output compare functions ................................................65 Unbuffered output compare timing diagram .......................................66 Unbuffered PWM functions .................................................................80 Unbuffered PWM mode and level selection .......................................86 Unbuffered PWM timing diagram .......................................................82 Using the HC708XL36 DMA with the TIM08 ....................................144 W Wait mode ........................................................................................116 TIM08 Reference Manual — Rev. 1.0 MOTOROLA Index For More Information On This Product, Go to: www.freescale.com 195 Freescale Semiconductor, Inc. Index Freescale Semiconductor, Inc... TIM08 Reference Manual — Rev. 1.0 196 Index For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 TIM08RM/AD For More Information On This Product, Go to: www.freescale.com ...
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