Digital systems and circuits

Digital systems and circuits - EEE 433/591(FALL 2010)...

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EEE 433/591(FALL 2010) DIGITAL SYSTEMS AND CIRCUITS Lab # 3 – Delay optimization and implementation of a logic path Professor: Dr.Islam Rajesh Yasam (ASU ID# ) Srinidhi Shreedhara (ASU ID # 1202836383) December 7, 2010 I. Introduction A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2 n , binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Most kinds of random-access memory use a n-to-2n decoder to convert the selected address on the address bus to one of the row address select lines. The decoder used here is a 3:8 decoder. The register used is a positive edge triggered master-slave flipflop. The edge- triggered flipflop is built from two D-type level-triggered latches (see the previous applets). Both latches are enabled with opposite polarity of the clock signal: The second (or slave) latch is controlled by the clock signal, while the first (or master) latch is enabled by the negated clock. As a result of this wiring of the clock signal,
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This note was uploaded on 02/13/2011 for the course EE 433 taught by Professor Dr.islam during the Fall '10 term at SUNY Buffalo.

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Digital systems and circuits - EEE 433/591(FALL 2010)...

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