SRAM for Digital Signal Processing

SRAM for Digital Signal Processing - San Jose State...

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San Jose State University SRAM 1 SRAM IP for DSP/SoC Projects By: Irina Vazir Prabhjot S. Balaggan Sumandeep Kaur Cailan Shen Project Advisor: Dr. David Parent
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San Jose State University SRAM 2 Table of Contents 1. Title page………………………………………………………………….1 2. Table of contents………………………………………………………….2 3. Technical Specifications……………………………………………….….3 4. SRAM Description…………………………………………………. .…. .. . 5 5. Design……………………………………………………………………. .7 a. static RAM cell………………………………………. ..………………. .8 b. precharge circuit…………………………………………………… …. 11 c. Sense amplifiers. ..………. ..…………….……………………………. ..13 d. mux design ……………………………………………………………16 e. One write and read cell ………………………………………………. .20 f. One column ……………………. .……………………. ..……………. ..24 g. Decoder …………………. ..…………………………………………. .27 h. SRAM system…………………………………………………………37 6. Test and Results ………………………………………………………. ..42 7. References…………………………………………………………. ........ 50
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San Jose State University SRAM 3 Technical Specifications: Features Organization: 8-bit X 8-bit SRAM IC Storage Capacity: 64 bits 40 Pin DIP Package: Figure 1 5 V Supply TTL Compatible Logic Pins On chip frequency: 20 MHz SRAM implemented using the full CMOS 6-T configuration Operating Temperature: 27 0 C Fabrication Technology: AMI06 (0.6 um process) Figure 1: 40 Pin DIP Package
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San Jose State University SRAM 4 Pin Assignments Pin # Pin Name Description 1 NC No Connect 2 NC No Connect 3 NC No Connect 4 NC No Connect 5 NC No Connect 6 NC No Connect 7 NC No Connect 8 NC No Connect 9 NC No Connect 10 A2 Decoder Address bit(MSB) 11 A1 Decoder Address bit 12 A0 Decoder Address bit(LSB) 13 D0 Data In/Out(LSB of a byte) 14 D1 Data In/Out 15 D2 Data In/Out 16 GND Ground 17 NC No Connect 18 NC No Connect 19 NC No Connect 20 NC No Connect 21 NC No Connect 22 NC No Connect 23 NC No Connect 24 CLK Clock Enable 25 D3 Data In/Out 26 D4 Data In/Out 27 D5 Data In/Out 28 D6 Data In/Out 29 D7 Data In/Out(MSB of a byte) 30 CS Chip Select 31 NC No Connect 32 RE Read Enable 33 NC No Connect 34 NC No Connect 35 NC No Connect 36 NC No Connect 37 WE Write Enable 38 NC No Connect 39 NC No Connect 40 VDD Power +5V Table 1: Pin assignments
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San Jose State University SRAM 5 SRAM Description: 8-bit X 8-bit SRAM IC was designed for future DSP/SoC applications. The SRAM IC is R/W memory circuit that permits the modification (writing) of data bits to
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This note was uploaded on 02/13/2011 for the course EE EE 480 taught by Professor Dr.davidparent during the Fall '09 term at San Jose State University .

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SRAM for Digital Signal Processing - San Jose State...

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