Lecture 24 - ta’tion Pad E gineer’s Compu 3.10.937 811E...

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Unformatted text preview: ta’tion Pad E gineer’s Compu 3.10.937 811E In! 1:3 .5 R0 . ‘L 1‘}, Inn g (Vl‘n “1-?2— = I5 R0 V0 it”; * ~2- <W ~ W fig. + 10. = a- I» [if ‘7 Rec 6. KC Vo 2%(g‘; 7%:— - 7%: VFAZ zvodv" V} Z ‘2 A .1; 5.2. was“) " R.” Recx 9 A”’?§i) My» “GK/40f /X'Hf/Ih¢;f- (an/ark}: ,0 $7 Poll—j Pm}, G/ezb’uflfg éfifl‘, Dec- 1003. i i l I 2N resistors 2x2” Resistors (all equal sizes) raw.) ' Fi . 12.12 Binary-array charge-redistribution D/ A converter. Shift register Switch network To DIA Fig. 12.19 Dynamically matching current sources for 6 M55. 2Nresislors (all equal sizes) 3 to 1 ol 8 decoder ‘Vrel Fig. 12.7 Binary—weighted Lbit resistor D/A converter. b b b v = -R v ("Li—in.) out F rel 2R 4H 8H RF (12.2) = _Vrel in R where l3.n = b,2"+b22'2+b32'3+ (12.3) Fig. 12.9 R—2K resistance ladder. I, I ‘ RI K van! 12 I = t I. 12 I.+I2 I t Fig. 12.14 Glitches. II represents the M53 current, and 12 represents the sum of the N — 1' [SB currentsl Here, the M53 current turns 0“ Slightly eady, causing a glitch of zero current. l 1 I a, Huh, ,_ _.,. _ ~ 13.2 SuccessiveApproximafion Converters Successive-approximation register (SAR) and control logic b 9 Bout N VD“ BH’LM/ air/V “A > [(9 Eff «66W? flaw)“ WW1.- fl/zécé (74” 44v 2", Laue/J . . i i i i ) 3 a x | i I . H74 C/wf 47,036 r 2 N4 Cm van’é/S (2"—1)toN encoder Fagi‘: [aloe/4 6764 M - Wust V 3 i i :1 Fig. 13.16. A 3-bit flash A/D oomerler. i % I f I i l I 3 i 5 i i ¥ i '50 SHEETS 22-142 100 SntETS 122-144 SHEETS 22-141 . ‘3') gig/MFA? "FM: per-I M-:w(.amd— MW? (75¢ Mf‘véf. OS‘IeT’lO a 4 Tia» SNKMA’; =~ c.02-N +1.76: + [6 /7JM (0:12) a é'n. +1.? + 2.0 = 94cm (Wot: M ouwswfig alga SM IJJQN; «(via/«amly, MMMVIZM JC'fl‘rv I} N=l/ -.‘S~Nfl,«4.,¢ '56 +2 + 20 = 28 0(3 ijao/f 50 SHEETS 00 SHEETS 22 141 22-142 1 22- AMMD 144 200 SHEETS Prefix/1 m Rea/6 V?“ ’-'- rfl—um t‘:za/Z’Zm' 10029? is «ML/“5,,- [Oat-0W 2: 5%,! , +0 + 714% Ml/X/‘mw (Sinus 05M) f};d¢o€ foal)” .‘5 7. . ZNA Vex P . z YMAZ 1 ) Pamaf : z =_—47 SIMA‘A 8 2M 1 3 ZN .50 {AIRch 18A LLOSR or [0 [ojlof—vi- Z 0;]? 1‘ | c60(13 ' 78cm (28 2943 “’13 “sde 52': a c. , ‘ mi /2. ‘ wa S/ecfi-J clams/’9,- . ~£/z f +50. 5. The Delta Sigma Modulator The delta sigma modulator is the core of delta sigma converters. As mentioned above it produces a bitstream. The average level of this bitstream represents the input signal level. A simple analogue first order delta sigma modulator blbck diagram looks like this: ' Difference Integrator Comparator Latch Bitstream Out 1-Bit DAC Figure 2 - Block Diagram of a First Order Analogue Delta Sigma Modulator Please notice that due to the negative feedback loop the average(!) output level at the l-Bit DAC must always be equal to the input signal level. The digital counterpart looks just as simple: Bitstream Out l-Bit DDC I Figure 3 - Block Diagram of a First Order Digital Delta Sigma Modulator ...
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Lecture 24 - ta’tion Pad E gineer’s Compu 3.10.937 811E...

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