ANSFB - E C E 4 1 7 5 B F in a l 5 -1 -0 9 E I GH T PR O B...

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ECE 4175B Final 5-1-09 Page 1 of 3 High 100 EIGHT PROBLEMS Upper quarter 84 Open book, open notes Median 74 Lower quarter 67 Low 33 1. [ ] I have completed the CIOS course evaluation. [5%] [ ] I have not completed the CIOS course evaluation. 2. When the 4321 chip is connected to several I C devices, the two pins SDA and SCL normally idle high 2 when no communication with the devices is taking place. [12%] a. To begin a message, the 4321 chip clears the SDA pin and then clears the SCL pin before sending the first byte of the message. What is going on and why? The 4321 chip is sending a “start condition” to the I C devices to “frame” the multiple- 2 byte message . b. While a multiple-byte message is being sent from the 4321 chip to one of the I C devices, how does the 2 selected I C device respond back to the 4321 chip? 2 After each eight bits sent to it, it pulls the SDA line low during the ninth bit time to acknowledge reception. c. At the completion of the multiple-byte message being sent from the 4321 chip to one of the I C devices, 2 what does the 4321 chip do before beginning to send the bytes of a new multiple-byte message to another device? Why does the 4321 chip do this? It raises SCL followed by raising SDA for “stop condition,” to complete the framing of the multiple-byte message. Then it begins the new multiple-byte message with the new start condition. 3. After doing the useful stuff in the main loop, you sometimes use the sleep mode before returning to the beginning of the main loop. For other applications you might use the idle mode before returning to the [16%] beginning of the main loop. a. Can awakening from the sleep mode be implemented using Timer1 clocked by the internal (Fcpu = 1 MHz) clock? [ ] Yes [ x ] No Explain below. Clocking of Timer1 stops in sleep mode
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ANSFB - E C E 4 1 7 5 B F in a l 5 -1 -0 9 E I GH T PR O B...

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