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M16_3_ch6 - DESIGN OF MULTILEVEL NETWORKS 1 TRANSFORMATIONS...

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1 DESIGN OF MULTILEVEL NETWORKS TRANSFORMATIONS TO SATISFY CONSTRAINTS - number of gate inputs - network size - network delay DESIGN OF NETWORKS WITH xor and xnor GATES DESIGN OF NETWORKS WITH multiplexers ( mux es) Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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2 DESIGN MORE COMPLEX THAN FOR TWO-LEVEL NETWORKS NO STANDARD FORM SEVERAL REQUIREMENTS HAVE TO BE MET SIMULTANEOUSLY SEVERAL OUTPUTS HAVE TO BE CONSIDERED CAD TOOLS (logic synthesis) USED Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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3 A DESIGN PROCEDURE 1. OBTAIN SP or PS EXPRESSIONS FOR THE FUNCTIONS OF THE SYS- TEM 2. TRANSFORM THE EXPRESSIONS (or the corresponding two-level net- works) so that the requirements are met 3. REPLACE and and or GATES BY nand and nor WHEN APPROPRIATE SEVERAL ITERATIONS MIGHT BE NEEDED Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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4 TYPICAL TRANSFORMATIONS TO MEET NETWORK REQUIREMENTS SIZE OF NETWORK: number of gates and number of gate inputs NUMBER OF GATES REDUCED BY 1. FACTORING 2. SUBEXPRESSIONS SHARED BY SEVERAL NETWORK OUTPUTS Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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5 EXAMPLE 6.1: 1-BIT COMPARATOR INPUTS: x, y ∈ { 0 , 1 } c ∈ { GREATER, EQUAL, LESS } OUTPUT: z ∈ { GREATER, EQUAL, LESS } FUNCTION: z = GREATER if x > y or ( x = y and c = GREATER ) EQUAL if x = y and c = EQUAL LESS if x < y or ( x = y and c = LESS ) Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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6 Example 6.1: Comparator (cont.) x i y i x i y i 1-BIT COMPARATOR z 1 z 0 z 2 c 1 c 0 c 2 (b) 1-BIT COMPARATOR x 0 y 0 1-BIT COMPARATOR 1-BIT COMPARATOR 1-BIT COMPARATOR x 1 y 1 x 2 y 2 x 3 y 3 z 1 z 0 z 2 z 1 z 0 z 2 c 1 c 0 c 2 c 1 c 0 c 2 = 0 = 1 = 0 (c) 1-BIT COMPARATOR c z {GREATER, EQUAL, LESS} {GREATER, EQUAL, LESS} (a) Figure 6.1: COMPARATOR Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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7 Example 6.1: Comparator (cont.) CODING: c c 2 c 1 c 0 z z 2 z 1 z 0 GREATER 1 0 0 EQUAL 0 1 0 LESS 0 0 1 x, y 00 01 10 11 100 100 001 100 100 c 010 010 001 100 010 001 001 001 100 001 z Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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8 Example 6.1: Comparator (cont.) SWITCHING EXPRESSIONS: z 2 = xy 0 xc 2 y 0 c 2 G z 1 = ( x 0 y )( x y 0 ) c 1 E z 0 = x 0 y x 0 c 0 yc 0 S RESULTING TWO-LEVEL NETWORK: - 7 and and 4 or gates - 22 equivalent gates - 25 gate inputs Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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9 REDUCING NETWORK SIZE (cont.) DEFINE: t = ( x y 0 ) w = ( x 0 y ) z 2 = xy 0 tc 2 z 1 = twc 1 z 0 = x 0 y wc 0 SIZE: 18 EQUIVALENT GATES FURTHER REDUCTION: NAND NETWORK – 9 EQUIVALENT GATES Introduction to Digital Systems 6 – Design of Multi-Level Gate Networks
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