M16_3_discussion3 - 4 Shannon s decomposition f(x n-1 x n-2...

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Discussion Note EEM16 Week3 1. Two-level gate networks with multiple outputs Design a 7-segment decoder to display a binary coded decimal (BCD) digit. 2. Two-level gate networks with 5 variables Design a single-error detector for the 2-out-of-5 code. The input is a digit in 2-out- of-5 code. The output is 0 if the number of 1 s in the input is 2. 3. Networks with XOR gates Ex. 6.7 Design the one-bit comparator using XOR and NAND gates only.
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Unformatted text preview: 4. Shannon s decomposition f(x n-1 , x n-2 , , x ) = f(x n-1 , x n-2 , , 1) x + f(x n-1 , x n-2 , , 0) x Ex. 6.9 Implement the following gates with 2-input MUX, assuming that complemented and uncomplemented variables are available: 2-input OR, 2-iinput NOR, 3-input NAND, XOR, and XNOR....
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