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Unformatted text preview: EE115C – Homework #6 Due 12 noon 12/05/2008 Problem #1 Wires A trace of metal-5 wire has characteristics of C W ’ (per length) = (0.15+0.05*width) fF/ µ m, and R W (a) For a 1.0- µ m wide wire trace, determine the delay for a trace with length of 1mm, 2mm, and 3mm. Assume that the trace is driven by an inverter of size W ’ (per length) = (0.15/width) Ω / µ m. The “width” in the equations are with units of microns. P =10 µ m and W N =4 µ m. The same inverter is at the end of the trace. Assume that C’ G =2fF/ µ m, C’ D =1fF/ µ m, R’ N =1.0k Ω- µ m and R’ P (b) If the 3-mm long trace in part-(a) has inverters of the same size as part-(a) inserted every 1mm. Determine the delay through the 3mm wire. =2.5k Ω- µ m. (c) What is the optimal inverter size to minimize delay? Note that this was not covered in lecture, but is in your textbook. Note the importance of buffer insertion to reduce delay! Problem #2 FlipFlops A positive edge triggered flipflop is shown below. All sizes are in microns (and minimum channel lengths). Assuming that R’ N_DN (NMOS pull-down)=1.0k Ω- µ m and R’ P_UP (PMOS pull-up)=2.5k Ω- µ m and ignore velocity saturation. Also assume that R’ N_UP (NMOS pull-up)=2.5*R’ N_DN (NMOS pull-down) and R’ P_DN (PMOS pull-down)=2.5*R’ P_UP (PMOS pull-up). And, C’(PMOS pull-up)....
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.
- Spring '10