20085ee115C_1_hw_2

20085ee115C_1_hw_2 - EE115C Homework #2 Due Date 10/22/2008...

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EE115C – Homework #2 Due Date 10/22/2008 Problem #1 Answer the following questions using the 90-nm CMOS technology provided. You are welcome to layout the structures in Cadence. (a) What is the minimum PMOS diffusion length (L DIFF ) with contacts? (b) Estimate the dimensions of a minimum sized transistor that has contacts on its diffusion. Be sure to account for gate extension in the direction of the width. Why is there a gate extension? (c) What is the minimum metal1-to-metal1 pitch (center to center) with contacts/vias? (d) What is the minimum metal9-to-metal9 pitch (center to center) with vias? Why is this different from (c). (e) What is the center-to-center pitch between the diffusion of a transistor? This is very useful in estimating the size of a layout. (f) Explain why the L eff (effective channel length) is shorter than the drawn channel length. Problem #2 Draw the switch logic for the following logical function, assume that true and complement inputs are available: (a) f = (a xnor b) c
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20085ee115C_1_hw_2 - EE115C Homework #2 Due Date 10/22/2008...

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