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20085ee115C_1_hw_3

# 20085ee115C_1_hw_3 - EE115C Homework#3 Due Date In-Class(No...

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EE115C – Homework #3 Due Date 10/29/2008 In-Class (No Late Homework Accepted) Problem #1 (a) Design a single Static CMOS gate with the following function (without sizing) f = ((a+b)c+d)’ (b) Assuming no velocity saturation and λ =0, size the devices for roughly equal rise and fall delays for all input-to-output paths. Let µ N C OX =2.5 µ P C OX . Let W D to be the size of the NMOS device whose gate input is “d”. Size all devices relative to W D (c) Assume that V . Use equal widths for stacked devices. DD =1.0V, V TN =-V TP =0.2V, L eff =50nm (both PMOS and NMOS), µ N C OX =2.5 µ P C OX , E CN =6V/ µ m, E CP =8V/ µ m, λ P =0.3 V -1 , and λ N =0.5V -1 (d) Using the same assumption as part (c), resize the devices of the logic gate for equal rise and fall delays. Use W . Determine the P:N ratio of an inverter for roughly equal rise and fall resistance. DX to be the size of the NMOS device whose gate input is “d”. Size everything relative to W DX Problem #2 . Use equal widths for stacked devices.

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