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Unformatted text preview: EE115C Homework #3 Due Date 10/29/2008 InClass (No Late Homework Accepted) Problem #1 (5+15+10+15) (a) Design a single Static CMOS gate with the following function (without sizing) f = ((a+b)c+d) (b) Assuming no velocity saturation and l =0, size the devices for roughly equal rise and fall delays for all inputtooutput paths. Let m N C OX =2.5 m P C OX . Let W D to be the size of the NMOS device whose gate input is d. Size all devices relative to W D . Use equal widths for stacked devices. (c) Assume that V DD =1.0V, V TN =V TP =0.2V, L eff =50nm (both PMOS and NMOS), m N C OX =2.5 m P C OX , E CN =6V/ m m, E CP =8V/ m m, l P =0.3 V1 , and l N =0.5V1 . Determine the P:N ratio of an inverter for roughly equal rise and fall resistance. (d) Using the same assumption as part (c), resize the devices of the logic gate for equal rise and fall delays. Use W DX to be the size of the NMOS device whose gate input is d. Size everything relative to W DX . Use equal widths for stacked devices. Problem #2...
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.
 Spring '10
 N/A
 Gate

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