20085ee115C_1_hw_4_new_sol

20085ee115C_1_hw_4_new_sol - EE115C Homework #4 Due @5pm on...

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EE115C – Homework #4 Due @5pm on 11/04/2008 Turn in at 56-147A EIV No Late Homework Accepted Problem #1 Delay Calculation of a Logic Gate For the logic gate shown above, calculate the delay of this logic gate from a transition of the D input to the output. You may assume that A=L, B=H and C=H. Do this for both rising and falling output transitions. Use the RC time-constant method where the resistance is calculated by finding the equivalent width of the PMOS/NMOS network using l * and finding the R P ’ and R N ’ of the equivalent inverter. You can assume that this logic gate is driving a logic gate with total input width (PMOS and NMOS combined) of 20 m m. For this problem, assume that V DD =1.0V, V TN =-V TP =0.2, L eff =50nm (both PMOS and NMOS), C G ’=2fF/ m m, C D ’=1.0fF/ m m, l N =0.5V -1 , l P =0.3V -1 , E CN =6V/ m m, E CP =8V/ m m, and m N C OX =2.5 m P C OX =125 m A/V 2 . Ignore any sharing of the diffusions.
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Problem #2 Logical Effort Assume that V DD =1.0V, V TN =-V TP
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20085ee115C_1_hw_4_new_sol - EE115C Homework #4 Due @5pm on...

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