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20085ee115C_1_hw_5

20085ee115C_1_hw_5 - EE115C Homework#5 Due In-Class on...

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EE115C – Homework #5 Due In-Class on 11/19/2008 Problem #1 Delay Comparison Consider 4 designs of a 6-input OR function as shown below. Develop an expression for the delay of each path if the path electrical effort is H. Which of the 4 design is fastest for H=1? for H=5? for H=20? Explain your conclusions intuitively. Assume static CMOS implementations of the gates and that β = µ =2.5, no velocity saturation, λ =0, and C D ’/C G ’=p inv =0.5. Problem #2 A three-input XNORT gate (see inset) works like a two-input NOR as long as input A is high; otherwise, the output is stuck high. Implement the XNORT gate in complementary CMOS, and size all transistors. Use the same size for series stacked devices and choose sizes so that the gate has equal rise and fall resistances. Assume that V DD =1.0V, V TN =-V TP =0.2, µ N =2.5 µ P , λ =0, and ignore velocity saturation. (a) Find the logical effort associated with each input for the XNORT gate. (b) For the logic path from node (1) to node (2) shown in the figure, find the path branching effort, path electrical effort, path logical effort, and total path effort. The letter associated with the gate represents the input capacitance for the critical path input for the corresponding logic gate.

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(c) What is the optimum effort per stage for minimizing delay? Assume that all
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