20085ee115C_1_hw_5_sol3

# 20085ee115C_1_hw_5_sol3 - EE115C Homework #5 Due In-Class...

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EE115C – Homework #5 Due In-Class on 11/17/2008 Problem #1 Delay Comparison (20) Consider 4 designs of a 6-input OR function as shown below. Develop an expression for the delay of each path if the path electrical effort is H. Which of the 4 design is fastest for H=1? for H=5? for H=20? Explain your conclusions intuitively. Assume static CMOS implementations of the gates and that b = m =2.5, no velocity saturation, l =0, and C D ’/C G ’=p inv =0.5.

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Problem #2 (10 + 10) A three-input XNORT gate (see inset) works like a two-input NOR as long as input A is high; otherwise, the output is stuck high. Implement the XNORT gate in complementary CMOS, and size all transistors. Use the same size for series stacked devices and choose sizes so that the gate has equal rise and fall delays. Assume that V DD =1.0V, V TN =-V TP =0.2, m N =2.5 m P , l =0, and ignore velocity saturation. Find the logical effort associated with each input. (a) For the logic path from node (1) to node (2) shown in the figure, find the

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## This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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20085ee115C_1_hw_5_sol3 - EE115C Homework #5 Due In-Class...

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