115C_1_ee115c_04

115C_1_ee115c_04 - Cost of IC Design 1 Cost of Integrated...

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1 Cost of IC Design
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2 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs – fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor indirect costs (the company overhead) Recurrent costs – variable silicon processing, packaging, test proportional to volume proportional to chip area
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3 NRE Cost is Increasing
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4 Total Cost Cost per IC Variable cost volume cost fixed IC per cost variable IC per cost + = yield test final packaging of cost test die of cost die of cost cost variable + + =
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5 Die Cost Single die Wafer Going up to 12” (30cm) yield die * per wafer dies wafer of cost die of cost = From: http://www.amd.com
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6 Yield % 100 per wafer chips of number Total per wafer chips good of Number × = Y yield Die per wafer Dies cost Wafer cost Die × = ( ) area die 2 diameter wafer area die diameter/2 wafer per wafer Dies 2 × × π × π =
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7 Defects α α × + = area die area unit per defects 1 yield die α≈ 3, complexity of mfg. process defects per unit area = 0.5 to 1 /cm 2 cost of die = f (die area) 4
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8 Some Examples (1994) $417 9% 40 296 1.5 $1500 0.80 3 Pentium $272 13% 48 256 1.6 $1700 0.70 3 Super Sparc
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_ee115c_04 - Cost of IC Design 1 Cost of Integrated...

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