115C_1_ee115c_04a_fab

115C_1_ee115c_04a_fab - Inverter Cross-section q Typically...

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0: Introduction Slide 25 CMOS VLSI Design Inverter Cross-section q Typically use p-type substrate for nMOS transistors q Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND V DD n+ p+ SiO 2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
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0: Introduction Slide 26 CMOS VLSI Design Well and Substrate Taps q Substrate must be tied to GND and n-well to V DD q Metal to lightly-doped semiconductor forms poor connection called Shottky Diode q Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND V DD n+ p+ substrate tap well tap n+ p+
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0: Introduction Slide 27 CMOS VLSI Design Inverter Mask Set q Transistors and wires are defined by masks q Cross-section taken along dashed line GND V DD Y A substrate tap well tap nMOS transistor pMOS transistor
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0: Introduction Slide 28 CMOS VLSI Design Detailed Mask Views q Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
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0: Introduction Slide 29 CMOS VLSI Design Fabrication Steps q Start with blank wafer q Build inverter from the bottom up q First step will be to form the n-well – Cover wafer with protective layer of SiO 2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO 2 p substrate
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_ee115c_04a_fab - Inverter Cross-section q Typically...

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