115C_1_ee115c_04b_layout

115C_1_ee115c_04b_layout - Gate Layout q Layout can be very...

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1: Circuits & Layout Slide 45 CMOS VLSI Design Gate Layout q Layout can be very time consuming – Design gates to fit together nicely – Build a library of standard cells q Standard cell design methodology – V DD and GND should abut (standard height) – Adjacent gates should satisfy design rules – nMOS at bottom and pMOS at top – All gates include well and substrate contacts
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1: Circuits & Layout Slide 46 CMOS VLSI Design Example: Inverter
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1: Circuits & Layout Slide 47 CMOS VLSI Design Example: NAND3 q Horizontal N-diffusion and p-diffusion strips q Vertical polysilicon gates q Metal1 V DD rail at top q Metal1 GND rail at bottom q 32 λ by 40 λ
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1: Circuits & Layout Slide 48 CMOS VLSI Design Stick Diagrams q Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers
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1: Circuits & Layout Slide 49 CMOS VLSI Design Wiring Tracks q A wiring track is the space required for a wire
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_ee115c_04b_layout - Gate Layout q Layout can be very...

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