115C_1_ee115c_07_08

# 115C_1_ee115c_07_08 - Gate Sizing 1 Ratio of Sizing for P...

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1 Gate Sizing

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2 Ratio of Sizing for P and N Networks Default goal: equal delays for different transitions. Size P’s to compensate for mobility C OX , V T , L are roughly the same. Make the Pull-up and Pull-down resistances equal R N /R P = 1 Classically, μ P W P / μ N W N = k β = 1 , k = mobility ratio, β = P:N ratio W P /W N = μ N / μ P Happens to be approximately the same as making logical threshold V THL = V DD /2. To account for velocity saturation and channel-length modulation. W I R DRV μ / 1 / 1 5 1 2 6 1 5 1 2 6 CP ND D PP D D T P C P N P CN NN D D T N C N PD D EL V WV V E R R V E V λ ⎛⎞ +− ⎜⎟ ⎝⎠ == −−
3 Classical Gate Sizing For stack devices, the total resistance can be used to find the equivalent device width of a single device. Or, use total resistance to find the size of each stack device. Need to assume sizing relationship within stack. Default is W 1 =W 2 =W 3 123 * min min 1 min min min * 11 23 * 1 1 TOT M M M equiv M M MM Me q u i v RR R R LL WW L W λ =++ = =+ + = C M 1 M 2 M 3 B A M O * 1 3 3 M MO W == = =

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4 Example of Classical Gate Sizing Complex gates can have multiple current paths depending on input combination. Default case is to make the resistances of all paths equal. C W W W W 2W 2W B A C W W 6W 6W B A W 6W Target β =2 M3 M2 M1
5 Asymmetric in Sizing Stacks We don’t need to assume W 1 =W 2 Example: 2W 1 =W 2 If equivalent inverter PMOS, W O =4, W 1 =6, W 2 =12 M 2 M 1 A B NOR Output 12 * 1 1 1 2 2 11 . 5 2 1.5 3 MM M M MO WW W W λ = =+ = = =

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## 115C_1_ee115c_07_08 - Gate Sizing 1 Ratio of Sizing for P...

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