115C_1_ee115c_09

115C_1_ee115c_09 - Delay Example 1 NAND Gate Delay Example(1 No velocity saturation and =0 Assume RN_DN=1k-m RP_UP=2k-m CGN=CGP= CG= 2fF/m CDN=CDP=

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1 Delay Example
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2 NAND Gate Delay Example (1) No velocity saturation and λ =0 Assume, R N_DN ’=1k Ω - μ m, R P_UP ’=2k Ω - μ m. C GN ’=C GP ’= C G ’= 2fF/ μ m, C DN ’=C DP ’= C D ’= 1fF/ μ m R N12 =R N1 + R N2 = R N_DN ’/(W N1 / λ *) = 1k Ω - μ m /(2 μ m/2) = 1k Ω R P = R P_UP ’/(W P ) = 2k Ω - μ m /(3 μ m) = 0.67k Ω C LOAD = C self + C gate C self = C D ’*(3 + 2) μ m (sharing) or C D ’*(6 + 2) μ m (not sharing) C gate = C G ’*(12 + 6) μ m t NANDpull_up = 0.69*0.67k*(41f) = 18.8ps t NANDpull_dn = 0.69*1k*(41f) =28.3ps R P out R N1 R N2 out C Load C Load Pull-Down Pull-Up 6 μ 12 μ out in 1 2 μ 3 μ in 2 2 μ 3 μ in 2 in 1 Sharing
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3 NAND Gate Delay Example With velocity saturation E c L=0.3 and λ =0.5 Calculate χ = W 0 /W N1 = 0.57 R N12 = R N_DN ’/( χ W N1 ) = 1k Ω - μ m /(0.57*2 μ m) = 0.88k Ω R P and C LOAD doesn’t change. t NANDpull_dn = 0.69*0.88k*(41f) =24.9ps
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4 Fan-In and Fan-Out There are several definitions for the same terms. Fan-In The number of inputs An indication of the input load that the gate presents to a predecessor gate. Because the series stack is roughly the number of inputs Later we will use Logical Effort to embed this concept. Fan-Out The number of gates driven by the gate An indication of the capacitive loading of a gate Depends on the type of gate. Typically normalize the loading to the gate capacitance of an inverter with equal drive strength as the gate. FO = C LOAD /C INV , where C INV = C G ’(W P +W N ) and R INV = R PULL_UP/DN of the logic gate
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5 Logical Effort
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6 Logical Effort Delay = (0.69) R gate (C load + C self ) =(0.69) (R gate C load + R gate C self ) Logical Effort basic equation: d = f + p d = delay/ τ o τ o = 0.69 R 0 C 0 f = effort delay (also fanout) p = parasitic delay. d = Delay/ τ = (R gate C load + R gate C self )/ R 0 C 0 Normalized to the delay of a FO-1 inverter (w/ no self load) Set R 0 = R gate , d = fanout + normalized parasitic. Key: d is a measure that is independent of process, voltage, temp .
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7 Logical and Electrical Effort Instead of just d = f + p, let f = gh g = logical effort (of a gate) Cost of implementing logic h = electrical effort Cost of driving a load. f= R gate C load /R 0 C 0 , p = R gate C self /R 0 C 0 Let R 0 = R inv where R inv = R gate , C 0 = C inv p = C self /C inv , f = C in C load /C in C inv C in is the gate’s input capacitance (for the particular input) g = C in /C inv Each gate (and each input of every gate) has different values. h = C load /C in Output to input capacitance ratio.
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8 Computing Logical Effort: g g is an unitless inherent characteristic of the gate Not a function of size of the gate. It is a function of the construction of the gate (connection and relative size between transistors) An indication of the “cost” of implementing the function.
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This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_ee115c_09 - Delay Example 1 NAND Gate Delay Example(1 No velocity saturation and =0 Assume RN_DN=1k-m RP_UP=2k-m CGN=CGP= CG= 2fF/m CDN=CDP=

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