115C_1_ee115c_12_13

115C_1_ee115c_12_13 - Adders 1 MIPS Processor Dataflow...

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1 Adders
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2 MIPS Processor Dataflow (courtesy of MIPS)
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3 Execution core Cache Integer and FP ALUs and MACs Tem p ( o C) Courtesy: R. Krishnamurthy (Intel) Processor thermal map ALUs: performance and peak-current limiters Goal: high-performance energy-efficient design ALUs Are Thermal Hotspots!
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4 Addition Logic Implementation Function within a 3-2 Adder Sum function S o =1 when Odd input 1’s S o = XOR(A,B,C i ) S o = A x B x C i Carry function C o =1 when 2 or more input 1’s C o = Majority(A,B,C i ) C o = AB+BC i +AC i ABC i S o C o 00000 00110 01010 01101 10010 10101 11001 11111
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5 0. Ripple-Carry Adder Sum is calculated starting at LSB Carry “ripples” from LSB into higher order bits to compute the sums and generate the next carry. Max delay t delay = t sum + (N-1) t carry Half Adder Full Adder A 0 B 0 S 0 C 1 A 1 B 1 S 1 C 2 Full Adder A n-1 B n-1 S n-1 C n C n-1
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6 SCMOS Mirror Adder Use carry to generate sum Note that Carry_b covers most of sum functions. Exclude all zeros, include all ones. Both Sum and Carry are symmetric functions. Inverted inputs results in inverted outputs. Sum’ = f N (a,b,c), Sum=f P (a’,b’,c’) f N =f P PMOS network is SAME as NMOS network. C i ABA B C o C o S o ABC A B C S o C i B A B C i S o C o 00000 00110 01010 01101 10010 10101 11001 11111
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7 Mirror Adder Stick Diagram C i AB V DD GND B C o AC i C o C i S
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8 A 3 FA FA FA Even cell Odd cell FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 B 3 S 3 C i ,0 C o ,0 C o ,1 C o ,3 C o ,2 Eliminating the Inverters Because both Sum (XOR) and Carry (Majority) are inversely symmetric functions. Inverted inputs result in inverted outputs. Implement without inverters in generating C o and S o . Move inverters to the outputs and inputs. Less gates in the critical path of carry May not be better…
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9 Propagate, Generate/Kill Propagating Carry from LSB to MSB is the limiting element. Look at Carry as a separate design. For every bit position: Carry in can be propagated When either A,B are 1’s Carry out can be generated When both A,B are 1’s Carry in can be killed When both A,B are 0’s Carry = AB + C(A+B) = AB + C(A x B) Generate = G = AB Propagate = P = A xor B (strict) P= A + B (loose) ABC i S o C o 00000 00110 01010 01101 10010 10101 11001 11111 Generate Propagate Kill
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10 1. Manchester Carry Chain using G & P
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115C_1_ee115c_12_13 - Adders 1 MIPS Processor Dataflow...

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