115C_1_ee115c_15

# 115C_1_ee115c_15 - Pass-Gate Analysis 1 Transmission Gate...

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1 Pass-Gate Analysis

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2 Transmission Gate Model Modeled with 2 resistors in parallel to represent the two transistors. Both are ON simultaneously. R P and R N depends on passing a HIGH or LOW value. XY A_b A A R P R N C S/D C S/D R P =R pull_upPMOS R N =R pull_upNMOS R P =R pull_downPMOS R N =R pull_downNMOS (lower R) (higher R) R P R N /(R P +R N )
3 T-Gate Delay Example t D2Q for latch = t d1 + t d2 Use Elmore delay to find t d1 For s rising Simplify our analysis R DRVP = R’ P_UP /3um R TGP = R’ P_UP /2um R TGN = R’ N_UP /2um C A ~ C D ’(3u + 1u) + 0.5C G ’ (2u + 2u)** C B ~ 0.5C G ’ (2u + 2u)** + + C G ’(3u + 1u) ** Note that the capacitances C A and C B approximates the capacitance of the pass gate to be half the gate loading capacitance For s falling R DRVN = R’ N_DN /3um R TGP = R’ P_DN /2um R TGN = R’ N_DN /2um q d ckb ck ckb ck t d1 s t d2 P:N=3:1 P:N=2:2 P:N=3:1 P:N=6:2 P:N=0.5:0.5 P:N=0.5:0.5 G2 G1 R DRVP C A q s R TGP R TGN C B t d1 t d2 G2

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4 Timing Analysis
5 Why Clocks? Means to synchronize. By allowing events to happen at known timing boundaries, we can sequence these events.

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## This note was uploaded on 02/09/2011 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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115C_1_ee115c_15 - Pass-Gate Analysis 1 Transmission Gate...

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