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project2

# project2 - CS m51A Logic Design of Digital Systems UCLA...

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CS m51A: Logic Design of Digital Systems UCLA Computer Science Department Fall 2009 Project 2 – Large Digital System Design Due Friday, December 4, 2009 12:00 Noon Sharp Provide a schematic that implements the multiplication of two floating point values, and outputs the resulting product in normalized form. We will use a simplified floating-point representation consisting of one sign bit, a 3-bit exponent , and a 4-bit significand (also called the fraction or, somewhat inaccurately, the mantissa ): The value represented by an 8-bit byte in this format is V = (-1) s · M ·2 E The S bit signifies the sign of the number. The 4-bit significant M ranges from (0000) = 0 to (1111) = 15, and the exponent ranges from (000) = 0 to (111) = 7. The following table shows the values corresponding to several FP representations. The last two rows of the above table demonstrate that some numbers have multiple FP representations. The preferred representation is the one in which the most significant bit of

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