Lec5_0126

# Lec5_0126 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 5 Yutao He 4532B Boelter Hall January 26 W’05

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.2 Outline Wrap-up - Combinational ICs Chapter 5 Minimization of two-level gate networks Summary
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.3 Big Picture of Chapter 3 Logic (Physical) Circuit Digital Systems CS EE 0 V L =0.0-0.8V 1 V H =2.0-3.3V V x V y V DD x y x y t t t t V x V y Load Factor Fanout Factor Size, Propagation Delay Current Dominated Technology: VLSI CMOS

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.4 Load Calculation Standard Load is defined for each CMOS family as the base unit Load factor is the load of the gate inputs usually given in the data sheet Total load is the sum of the load factors of all the inputs connected to one output Fanout factor is the maximal load that one output can take
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.5 Load Calculation - Example

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.6 Three-State Driver (Buffers) Symbol Function Implementation
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.7 Three-State Driver - Applications

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.8 The Data Sheet of A Logic Family
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L5.9 Design of Combinational Systems Decide: Inputs,Output, Function Step 1: Common Sense, Educated Guess Select: Encoding Scheme Step 2: Number Systems, Standard Fill in: Truth Table Step 3: Boolean Operations Write: Switching Expressions Step 4: Switching Algebra Implement: w/ 2-level Gate networks Step 5: Primitive Logic Gates

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CSM51A/EEM16-Sec.1 W’05 L5.10 Example - Modulo-8 Incrementer High-Level Specification: Input: 0 ≤ x ≤ 7 Output: 0 ≤ z ≤ 7
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Lec5_0126 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

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