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Lec7_0202 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 7 Yutao He [email protected] 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200 February 2 W’05
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.2 Outline Chapter Wrap-up: Programmable modules Chapter 6: Multiple-Level Networks Summary
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.3 Basic Technology: AND-OR, OR-AND, NAND-NAND, NOR-NOR Programmable modules PLAs PALs Basic Skills: K-Map Don’t cares Minterms Maxterms Quine-McCluskey Algorithm Boolean Algebra Design in Two-Level Logic - Review
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.4 Design with Programmable Modules Regular and standard structure Customized (programmed) for a particular function During the last stage of fabrication When incorporated into a system Flexible use and field upgrade Slower than fixed-function modules Common types: PLAs PALs CPLDs FPGAs
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.5 Programmable Logic Arrays (PLAs) Pre-fabricated building block of many AND/OR gates ”Programmed" by making or breaking connections among gates Programmable array block diagram for sum of products form •   •   • inputs AND Array •   •   • outputs OR Array product terms •   •   • PLA (n, p, m)
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.6 Logic Diagram of PLAs All possible connections available before "programming"
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.7 Alternative Representation Short-hand notation - don't have to draw all the wires
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L7.8 How to design with PLAs Step 1:
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  • Winter '07
  • ERCEGOVAC
  • Logic gate, Boelter Hall, Logic Synthesis, Minterms Maxterms, CSM51A/EEM16-Sec.1 W'05, Combinational Networks

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