Lec7_0202

Lec7_0202 - Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.1 CS...

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Unformatted text preview: Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.1 CS M51A/EE M16 Winter05 Section 1 Logic Design of Digital Systems Lecture 7 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200 February 2 W 0 5 Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.2 Outline Chapter Wrap-up: Programmable modules Chapter 6: Multiple-Level Networks Summary Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.3 Basic Technology: AND-OR, OR-AND, NAND-NAND, NOR-NOR Programmable modules PLAs PALs Basic Skills: K-Map Dont cares Minterms Maxterms Quine-McCluskey Algorithm Boolean Algebra Design in Two-Level Logic - Review Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.4 Design with Programmable Modules Regular and standard structure Customized (programmed) for a particular function During the last stage of fabrication When incorporated into a system Flexible use and field upgrade Slower than fixed-function modules Common types: PLAs PALs CPLDs FPGAs Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.5 Programmable Logic Arrays (PLAs) Pre-fabricated building block of many AND/OR gates Programmed" by making or breaking connections among gates Programmable array block diagram for sum of products form inputs AND Array outputs OR Array product terms PLA (n, p, m) Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.6 Logic Diagram of PLAs All possible connections available before "programming" Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.7 Alternative Representation Short-hand notation - don't have to draw all the wires Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.8 How to design with PLAs...
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Lec7_0202 - Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W05 L7.1 CS...

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