Lec8_0207

Lec8_0207 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 8 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall February 7 W’05
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.2 Outline Administrative Matter Review: Design of combinational systems Chapter 4: Analysis of combinational systems Summary
Background image of page 2
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.3 Administrative Matter Quiz #2 Will be handed back on Wednesday Project #1 Will be assigned on Wednesday Class Grade Will be available via myUCLA gradebook
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.4 Design of Comb. Systems - Big Picture Specification Implementation Design Truth Table Switching Expression K-Map VHDL Timing Diagram Logic Diagram Net List Two-Level Logic AND-OR, OR-AND NAND-NAND, NOR-NOR Multi-Level Logic XORs Programmable Modules PLAs PALs Minimization Boolean Algebra K-Map Quine-McCluskey Algorithm
Background image of page 4
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.5 Analysis: Given a gate network of a system, find what the system does (binary level and high-level). Objectives: Verify the system’s function Debug the implementation Optimize the system implementation Analysis of Comb. Systems - Big Picture Implementation Specification Analysis
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.6 Validity analysis Is the implementation a valid combinational gate network? Functional analysis What does the network do? Binary-level switching function High-level meaningful statement Performance analysis How fast/well does the network perform? Delays, fanout factors, input load factors
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 34

Lec8_0207 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online