Lec8_0207

# Lec8_0207 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 8 Yutao He 4532B Boelter Hall February 7 W’05

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.2 Outline Administrative Matter Review: Design of combinational systems Chapter 4: Analysis of combinational systems Summary
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.3 Administrative Matter Quiz #2 Will be handed back on Wednesday Project #1 Will be assigned on Wednesday Class Grade Will be available via myUCLA gradebook

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.4 Design of Comb. Systems - Big Picture Specification Implementation Design Truth Table Switching Expression K-Map VHDL Timing Diagram Logic Diagram Net List Two-Level Logic AND-OR, OR-AND NAND-NAND, NOR-NOR Multi-Level Logic XORs Programmable Modules PLAs PALs Minimization Boolean Algebra K-Map Quine-McCluskey Algorithm
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.5 Analysis: Given a gate network of a system, find what the system does (binary level and high-level). Objectives: Verify the system’s function Debug the implementation Optimize the system implementation Analysis of Comb. Systems - Big Picture Implementation Specification Analysis

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L8.6 Validity analysis Is the implementation a valid combinational gate network? Functional analysis What does the network do? Binary-level switching function High-level meaningful statement Performance analysis How fast/well does the network perform? Delays, fanout factors, input load factors
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Lec8_0207 - CS M51A/EE M16 Winter'05 Section 1 Logic Design...

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