Lec11_0223

Lec11_0223 - CS M51A/EE M16 Winter'05 Section 1 Logic...

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 11 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall February 23 W’05
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.2 Outline Administrative Matters Chapter 7 Specification of Sequential Systems State Minimization
Background image of page 2
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.3 Administrative Matters Project #2 Is posted on the web Due on March 2 (Wednesday) Teamwork is allowed and encouraged Find your partner as early as possible Homework #7 Is posted on the web Midterm Will be handed back and discussed on Next Monday
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.4 Sequential Systems: Overview Basic Concepts Synchronous sequential systems Clocks States Finite state machines Mealy and Moore machines Specification Time behavior (I/O sequence) State transition table State diagram Minimization Analog Digital Sync. Async. Comb . Seq. (Hardware) Systems
Background image of page 4
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.5 Definition of Sequential Systems
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.6 Sync. Vs. Async. Sequential Systems Synchronous Asynchronous
Background image of page 6
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.7 Clock An independent periodic reference signal Provided by An internal crystal An external 60 Hz alternating current Make sure you know When is the present (t) When is the next (t+1) * back to the future When is the previous (t-1) * forth to the past
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.8 Time-Behavior Specification Behavior of a sequential system can be specified by a sequence of input(s)/output(s) pairs with respect to the clock signal Time t 0 1 2 . .. Input x i (t) Output z i (t)
Background image of page 8
Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L11.9 Example 7.1: Serial Decimal Adder Addition is performed one digit at a time, starting from the LSB Output is generated at each time instant As a result, a 8-digit serial decimal adder needs 8 clock cycles to finish the calculation s = x + y = 21638753+73652425 t 0 1 2 3 4 5 6 7 x(t) 3 5 7 8 3 6 1 2 y(t) 5 2 4 2 5 6 3 7 s(t) 8 7 1 1 9 2 5 9 c(t) 0 0 1 1 0 1 0 0
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Y. He @ 02/14/11
Background image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 33

Lec11_0223 - CS M51A/EE M16 Winter'05 Section 1 Logic...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online