Lec13_0302

Lec13_0302 - CS M51A/EE M16 Winter'05 Section 1 Logic...

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 13 Yutao He [email protected] 4532B Boelter Hall March 2 W’05
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.2 Outline Administrative Matters Basic sequential devices - Recap Design of sequential systems w/ FFs Analysis of sequential systems Timing Analysis Functional analysis
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.3 Administrative Matters Quiz #3 Given on Friday Closed-book/Closed-note You’ll be given FF Excitation Tables if they’re used Project #3 Is posted and due at 2pm March 11 (Friday), 2005 Midterm Solution Is posted
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.4 Latch and FF behavior is the same unless input changes while the clock is high D Q CLK positive edge-triggered flip-flop D Q G CLK Level-sensitive gated latch D CLK QFF Qlatch Loop feedback introduces “memory” capability
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.5 Edged-Trigged Flip-Flops Development of D-FF Level-sensitive used in custom integrated circuits Edge-triggered used in programmable logic devices Good choice for data storage register Historically J-K FF was popular but now never used Similar to R-S but with 1-1 being used to toggle output Good in days of TTL/SSI (more complex input function): D = JQ' + K'Q Not a good choice for PALs/PLAs as it requires 2 inputs Can always be implemented using D-FF Asynchronous preset and clear inputs are highly desirable on FFs Used at start-up or to reset system to a known clean state
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.6 Excitation Functions of Flip-Flops D Flip-Flop SR Flip-Flop JK Flip-Flop T Flip-Flop
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.7 Roadmap of Implementation w/ FFs Start with State Table Select FF Types Fill in Truth Table of FF inputs Simplify with K-Map Write up Switching Expressions Draw Networks (FFs+Gates)
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.8 Ex. 8.8 - Modulo-5 Counter Use T flip-flops to design a modulo-5 counter
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.9 Ex. 8.8 - Modulo-5 Counter (Cont’d) State Assignment State Transition Table 5, 6, and 7 are don’t cares!
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.10 Ex. 8.8 - Modulo-5 Counter (Cont’d) Truth Tables for T0,T1,T2 T Q Q CLK T Q Q CLK T Q Q CLK x y2 y1 y0 To Be Designed
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.11 Ex. 8.8 - Modulo-5 Counter (Cont’d) Switching Expressions K-Maps
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.12 Ex. 8.8 - Modulo-5 Counter (Cont’d)
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.13 Example 8.9
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.14 Example 8.9 (Cont’d)
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.15 Example 8.9 (Cont’d)
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.16 Example 8.9 (Cont’d) 00 01 10 11
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L13.17 Example 8.9 (Cont’d)
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Y. He @ 02/14/11
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This note was uploaded on 02/14/2011 for the course CS M51A taught by Professor Ercegovac during the Winter '07 term at UCLA.

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Lec13_0302 - CS M51A/EE M16 Winter'05 Section 1 Logic...

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