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Unformatted text preview: Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15 Yutao He [email protected] 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200 March 9 W ’0 5 Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.2 Outline • Recap  Combinational macro modules – Decoders – Encoders – Shifters • Combinational macro modules – Multiplexers – Demultiplexers • Chapter 11 Sequential Modules – Registers – Shift registers Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.3 Chapter 9  Overview Combinational Systems Gate networks (AND, OR, NAND, etc.) Chapters 26 Design Analysis Module networks (DEC/ENC, MUX/DEMUX, Shifter.) Chapter 9 • Basic Questions: – What are each module’s property? * inputs, outputs, functions (highlevel and binary level) – How to implement it using logic gates? – How to design a comb. system using these modules? – How to analyze a comb. system using these modules? Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.4 Multiplexer (MUX) EN E 2 nInput Multiplexer 1 2 n1 x x 1 x 2 n1 Data Inputs n1 s n1 s Selection Inputs z Data Output Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.5 Multiplexer  Specification HighLevel BinaryLevel Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.6 Multiplexer  Implementation (1) Implementation of MUX with AND/OR gates Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.7 Multiplexer  Implementation (2) Implementation of MUX with transmission gates Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.8 Multiplexer (Tree) Networks s = 9 s 3 s 2 s 1 s 0 = 1001 1 1 z = x 9 Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.9 Applications of MUXes nbit Simple Shifter Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.10 Applications of MUXes (Cont’d) 4bit Right3 Unidirectional Shifter Y. He @ 02/14/11 CSM51A/EEM16Sec.1 W’05 L15.11 Design Using MUXes • Key observations: – A 2 nInput MUX corresponds to a n input switching function. – Data outputs store output values of the switching function. – Selection inputs correspond to the inputs of the switching function....
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This note was uploaded on 02/14/2011 for the course CS M51A taught by Professor Ercegovac during the Winter '07 term at UCLA.
 Winter '07
 ERCEGOVAC

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