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Lec16_0314 - CS M51A/EE M16 Winter'05 Section 1 Logic...

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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.1 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 16 Yutao He [email protected] 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200 March 14 W’05
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.2 Outline Administrative Matters Recap Registers Shift Registers Chapter 11 – Sequential macro modules Counters
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.3 Administrative Matters HW# 9 Is posted and will be self-graded Describes how the topics in Ch. 11 and 12 will be tested The Final Is given on Friday A review session will be held on Wednesday Extra office hours will be scheduled My office hours this week Monday and Wednesday * 6-7:30pm Thursday * 7:30-9pm Graded work
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.4 Chapter 11 Sequential Modules Sequential Systems Flip-Flops (D, JK, SR, T FFs, etc.) Chapters 7-8 Design Analysis Module networks (Register, Shift Register, Counter) Chapter 11 Basic Questions: What are each module’s property? * inputs, outputs, functions (high-level and binary level) How to implement it using FFs and logic gates? How to design a sequential system using these modules? How to analyze a sequential system using these modules?
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.5 n-Bit Register
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.6 Shift Registers Shift Register CLK CTL m n Basic Types: Serial In/Serial Out (SI/SO): m=n=1 Serial In/Parallel Out (SI/PO): m=1, n> 1 Parallel In/Serial Out (PI/SO): m>1, n=1 Parallel In/Parallel Out (PI/PO): m, n > 1
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.7 Modulo-p Counter Modulo-p Counter CLK CTL n TC
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Y. He @ 02/14/11 CSM51A/EEM16-Sec.1 W’05 L16.8 Modulo-p Counter: High-Level Spec
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Y. He @ 02/14/11
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