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Syllabus - Prerequisites This course requires the knowledge...

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EEE 333: Hardware Design Languages and Programmable Logic Fall 2008, T Th, 1:30-2:45pm, Engineering Center G G224 Instructor Dr. Yu (Kevin) Cao, GWC 336, [email protected] Office Hours: T Th, 3:00-4:00pm, GWC 336 TA Ambika Kotthanahalli, [email protected] Course Introduction This course is an introduction to the VHDL language for contemporary design of ASIC and FPGA systems. The material covers CMOS digital logic, VHDL coding and modeling, synthesis and verification, and FPGA design basics. The comprehensive lectures will address the knowledge of a hardware-oriented VHDL premier, such as VHDL data types, testbenches, Finite State Machines (FSMs), and memory structures. The fundamental learning will be reinforced by realistic examples for each topic and by practical lab exercises. The knowledge gained in this course can be applied to any VLSI design by using a top-down design methodology.
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Unformatted text preview: Prerequisites This course requires the knowledge of basic circuit design and Boolean logic, such as CSE 101, ECE 100/200, EEE 101, CSE 120, or EEE 120. Text Book • The Designer’s Guide to VHDL , by Peter J. Ashenden, 2 nd Ed. • FPGA-Based System Design , by Wayne Wolf. Further Reading • HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog , by Douglas J. Smith. • Digital Integrated Circuits: A Design Perspective , by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, 2 nd Ed. ( http://bwrc.eecs.berkeley.edu/IcBook/ ) Grading Policy Letter Grade Homework (6): 18% A+: top 10% Lab (5): 20% A: > (average + 0.5 σ ) Midterm (2): 20%+20% A-: > average Final Exam (1): 22% B+: > (average – 0.5 σ ) B: > (average – σ ) B-: > (average – 1.5 σ ) C: > (average – 2 σ ) D: else...
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  • Spring '11
  • Logic gate, Field-programmable gate array, Application-specific integrated circuit, Hardware Design Languages and Programmable Logic, hardware-oriented VHDL premier

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