Lecture-01 - EEE 333 VHDL L-01 Introduction Fall 2008 ASU...

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1 EEE 333: VHDL, L-01 EEE 333: VHDL, L-01 Fall 2008, ASU Yu (Kevin) Cao, [email protected] , GWC 336 Introduction Introduction EEE 333, ASU, Y. Cao Lecture 01 - 2 - Highlight Highlight Course orientation Objective, textbook, assignments, and grading policy Acknowledgement: course materials from Professor Lawrence Clark, ASU VLSI design methodology History, today, and tomorrow Synthesis (top-down) vs. Custom (bottom-up) Handout: Syllabus and Tentative Schedule
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2 EEE 333, ASU, Y. Cao Lecture 01 - 3 - Basic Information Basic Information Instructor: Y. Kevin Cao, GWC 336 Office hour: T/Th, 3:00-4:00pm ; E-mail: [email protected] Textbook: The Designer’s Guide to VHDL , by Peter J. Ashenden, 2 nd Ed. (electronic version available) FPGA-Based System Design , by Wayne Wolf Other references (reserved in the library): HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog , by Douglas J. Smith Digital Integrated Circuits: A Design Perspective , by Jan M. Rabaey, et al. ( http://bwrc.eecs.berkeley.edu/IcBook/ ) Lab at GWC 273, with TA available Lectures etc. are available at http://my.asu.edu EEE 333, ASU, Y. Cao Lecture 01 - 4 - What will You Learn What will You Learn VHDL language for contemporary VLSI design, with practical applications to FPGA systems Content: CMOS digital synthesis, VHDL coding and modeling, combinational and sequential logic, architecture, and FPGA hardware Pre-requisite : basic understanding of CMOS digital circuits and Boolean logic Further study: digital circuit design, computer architecture, and computer-aided design (CAD)
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3 EEE 333, ASU, Y. Cao Lecture 01 - 5 -
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