Lecture-02 - EEE 333: VHDL, L-02 CMOS Technology and IC...

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1 EEE 333: VHDL, L-02 EEE 333: VHDL, L-02 Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu , GWC 336 CMOS Technology and IC Design CMOS Technology and IC Design EEE 333, ASU, Y. Cao Lecture 02 - 2 - Highlight Highlight ± MOSFET basics The structure and operation First-order model: a switch + a resistor ± CMOS logic: inverter Logic gate construction Static and dynamic behavior Delay model ± Interconnect and package ± Reading: Chapter 2 in Wolf’s book Further reading: Chapter 3 and 5 in Rabaey’s book
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2 EEE 333, ASU, Y. Cao Lecture 02 - 3 - Highlight Highlight ± MOSFET basics The structure and operation First-order model: a switch + a resistor ± CMOS logic: inverter – Logic gate construction – Static and dynamic behavior – Delay model ± Interconnect and package ± Reading: Chapter 2 in Wolf’s book – Further reading: Chapter 3 and 5 in Rabaey’s book EEE 333, ASU, Y. Cao Lecture 02 - 4 - 3D Perspective of a MOSFET 3D Perspective of a MOSFET Polysilicon/Metal Gate Aluminum/Copper ± MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor
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3 EEE 333, ASU, Y. Cao Lecture 02 - 5 - Technology Evolution Technology Evolution 50nm 2002 (90nm node) G a t e S o u r c D i n 15nm 2015 ? 1947 ???? ± New materials and structures to keep the scaling Improve carrier mobility (e.g., SiGe channel) Reduce gate/S/D resistance (e.g., metal-gate, Ge for S/D) Suppress gate and channel leakage (e.g., high-k insulator) EEE 333, ASU, Y. Cao
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Lecture-02 - EEE 333: VHDL, L-02 CMOS Technology and IC...

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