Lecture-09 - EEE 333: VHDL, L-09 Process Examples Fall...

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1 EEE 333: VHDL, L-09 EEE 333: VHDL, L-09 Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu , GWC 336 Process Examples Process Examples EEE 333, ASU, Y. Cao Lecture 09 - 2 - Highlight Highlight ± Register, Counter, and Shift Register ± Reading: Chapters 1-5 in Ashenden’s book
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2 EEE 333, ASU, Y. Cao Lecture 09 - 3 - Modeling Review: Architecture Modeling Review: Architecture architecture ARCHITECTURE_NAME of ENTITY_NAME is -- Declarations of signals, constants, functions, procedures go here -- Component declarations go here -- No variable declarations begin -- Concurrent statements go here (combinational logic) -- Conditional signal assignment -- Selected signal assignment -- Generate statements -- Component instantiation statements process_label: process [(sensitivity_list)] is process_declarations begin -- sequential statements end process [process_label]; end ARCHITECTURE_NAME; EEE 333, ASU, Y. Cao Lecture 09 - 4 - Process Statements Process Statements ± Syntax of Process process_label: process [(sensitivity_list)] is process_declarations begin sequential statement end process [process_label]; The process sensitivity list is an implicit “wait on sensitivity_list” at the end You can’t use both but must have one – otherwise the process will never be activated! ± Process
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Lecture-09 - EEE 333: VHDL, L-09 Process Examples Fall...

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