Lecture-04 - EEE 333: VHDL, L-04 Sequential Circuit Fall...

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1 EEE 333: VHDL, L-04 EEE 333: VHDL, L-04 Fall 2008, ASU Yu (Kevin) Cao, [email protected] , GWC 336 Sequential Circuit Sequential Circuit EEE 333, ASU, Y. Cao Lecture 04 - 2 - Highlight Highlight ± Sequential system ± Sequential logic design Elements: Latch and Flip-Flop Timing issues ± Reading: Chapter 2 in Wolf’s book Further reading: Chapter 7.1 and 7.2 in Rabaey’s book
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2 EEE 333, ASU, Y. Cao Lecture 04 - 3 - Highlight Highlight ± Sequential system ± Sequential logic design – Elements: Latch and Flip-Flop – Timing issues ± Reading: Chapter 2 in Wolf’s book – Further reading: Chapter 7.1 and 7.2 in Rabaey’s book EEE 333, ASU, Y. Cao Lecture 04 - 4 - Combinational Logic Units Combinational Logic Units ± Arithmetic Logic Unit (ALU) is the core of a microprocessor ± Is that enough to construct a system? FA FA FA FA A 0 B 0 S 0 A 1 B 1 S 1 A 2 B 2 S 2 A 3 B 3 S 3 Ci ,0 Co ,0 ( = Ci ,1) Co ,1 Co ,2 Co ,3 Cout a Sum Cin b
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3 EEE 333, ASU, Y. Cao Lecture 04 - 5 - A Digital Processor A Digital Processor ± Control: finite-state-machine, counters, etc. ± Datapath: adder, multiplier, shifter, etc. ± Memory: registers, RAM, ROM, etc. ± Others: I/O, switches, etc. MEMORY DATAPATH CONTROL INPUT-OUTPUT EEE 333, ASU, Y. Cao Lecture 04 - 6 - Control in a Synchronous System Control in a Synchronous System ±
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Lecture-04 - EEE 333: VHDL, L-04 Sequential Circuit Fall...

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